Imported Upstream version 17.05.2

[deb_dpdk.git] / drivers / net / mlx5 / mlx5_rxtx.h

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 5708c2a..450a569 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -114,7 +114,8 @@ struct rxq {
        unsigned int elts_n:4; /* Log 2 of Mbufs. */
        unsigned int port_id:8;
        unsigned int rss_hash:1; /* RSS hash result is enabled. */
-       unsigned int :9; /* Remaining bits. */
+       unsigned int mark:1; /* Marked flow available on the queue. */
+       unsigned int :8; /* Remaining bits. */
        volatile uint32_t *rq_db;
        volatile uint32_t *cq_db;
        uint16_t rq_ci;
@@ -132,11 +133,9 @@ struct rxq_ctrl {
        struct priv *priv; /* Back pointer to private data. */
        struct ibv_cq *cq; /* Completion Queue. */
        struct ibv_exp_wq *wq; /* Work Queue. */
-       struct ibv_exp_res_domain *rd; /* Resource Domain. */
        struct fdir_queue *fdir_queue; /* Flow director queue. */
        struct ibv_mr *mr; /* Memory Region (for mp). */
-       struct ibv_exp_wq_family *if_wq; /* WQ burst interface. */
-       struct ibv_exp_cq_family_v1 *if_cq; /* CQ interface. */
+       struct ibv_comp_channel *channel;
        unsigned int socket; /* CPU socket ID for allocations. */
        struct rxq rxq; /* Data path structure. */
 };
@@ -246,17 +245,24 @@ struct txq {
        uint16_t elts_head; /* Current index in (*elts)[]. */
        uint16_t elts_tail; /* First element awaiting completion. */
        uint16_t elts_comp; /* Counter since last completion request. */
+       uint16_t mpw_comp; /* WQ index since last completion request. */
        uint16_t cq_ci; /* Consumer index for completion queue. */
+       uint16_t cq_pi; /* Producer index for completion queue. */
        uint16_t wqe_ci; /* Consumer index for work queue. */
+       uint16_t wqe_pi; /* Producer index for work queue. */
        uint16_t elts_n:4; /* (*elts)[] length (in log2). */
        uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
        uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
-       uint16_t bf_buf_size:4; /* Log2 Blueflame size. */
-       uint16_t bf_offset; /* Blueflame offset. */
+       uint16_t inline_en:1; /* When set inline is enabled. */
+       uint16_t tso_en:1; /* When set hardware TSO is enabled. */
+       uint16_t tunnel_en:1;
+       /* When set TX offload for tunneled packets are supported. */
+       uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
        uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
+       uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
        uint32_t qp_num_8s; /* QP number shifted by 8. */
        volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
-       volatile struct mlx5_wqe64 (*wqes)[]; /* Work queue. */
+       volatile void *wqes; /* Work queue (use volatile to write into). */
        volatile uint32_t *qp_db; /* Work queue doorbell. */
        volatile uint32_t *cq_db; /* Completion queue doorbell. */
        volatile void *bf_reg; /* Blueflame register. */
@@ -274,9 +280,6 @@ struct txq_ctrl {
        struct priv *priv; /* Back pointer to private data. */
        struct ibv_cq *cq; /* Completion Queue. */
        struct ibv_qp *qp; /* Queue Pair. */
-       struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
-       struct ibv_exp_cq_family *if_cq; /* CQ interface. */
-       struct ibv_exp_res_domain *rd; /* Resource Domain. */
        unsigned int socket; /* CPU socket ID for allocations. */
        struct txq txq; /* Data path structure. */
 };
@@ -304,6 +307,12 @@ int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
                        const struct rte_eth_rxconf *, struct rte_mempool *);
 void mlx5_rx_queue_release(void *);
 uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
+int priv_rx_intr_vec_enable(struct priv *priv);
+void priv_rx_intr_vec_disable(struct priv *priv);
+#ifdef HAVE_UPDATE_CQ_CI
+int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+#endif /* HAVE_UPDATE_CQ_CI */
 
 /* mlx5_txq.c */
 
@@ -320,9 +329,12 @@ uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
+uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
+int mlx5_rx_descriptor_status(void *, uint16_t);
+int mlx5_tx_descriptor_status(void *, uint16_t);
 
 /* mlx5_mr.c */