New upstream version 18.11-rc1

[deb_dpdk.git] / drivers / net / qede / base / mcp_public.h

diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index 81ca663..13c2e2d 100644 (file)
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -1,9 +1,7 @@
-/*
- * Copyright (c) 2016 QLogic Corporation.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
  */
 
 /****************************************************************************
@@ -800,6 +798,7 @@ struct public_port {
 #define ETH_TRANSCEIVER_TYPE_4x10G                     0x1f
 #define ETH_TRANSCEIVER_TYPE_4x25G_CR                  0x20
 #define ETH_TRANSCEIVER_TYPE_1000BASET                 0x21
+#define ETH_TRANSCEIVER_TYPE_10G_BASET                 0x22
 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR     0x30
 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR     0x31
 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR     0x32
@@ -1259,6 +1258,17 @@ struct public_drv_mb {
  */
 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG         0x34000000
 #define DRV_MSG_SET_RESOURCE_VALUE_MSG         0x35000000
+#define DRV_MSG_CODE_OV_UPDATE_WOL             0x38000000
+#define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE    0x39000000
+#define DRV_MSG_CODE_S_TAG_UPDATE_ACK          0x3b000000
+#define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID      0x3c000000
+#define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME       0x3d000000
+#define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG       0x3e000000
+#define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT      0x3f000000
+#define DRV_MSG_CODE_OV_GET_CURR_CFG           0x40000000
+#define DRV_MSG_CODE_GET_OEM_UPDATES           0x41000000
+/* params [31:8] - reserved, [7:0] - bitmap */
+#define DRV_MSG_CODE_GET_PPFID_BITMAP          0x43000000
 
 /*deprecated don't use*/
 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED    0x02000000
@@ -1468,6 +1478,7 @@ struct public_drv_mb {
 
 /* Param: Password len. Union: Plain Password */
 #define DRV_MSG_CODE_ENCRYPT_PASSWORD          0x00360000
+#define DRV_MSG_CODE_GET_ENGINE_CONFIG         0x00370000 /* Param: None */
 
 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
 
@@ -1583,6 +1594,16 @@ struct public_drv_mb {
 #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET                0
 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK          0xFFFFFFFF
 
+#define DRV_MB_PARAM_ESWITCH_MODE_MASK  (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
+                                        DRV_MB_PARAM_ESWITCH_MODE_VEB |   \
+                                        DRV_MB_PARAM_ESWITCH_MODE_VEPA)
+#define DRV_MB_PARAM_ESWITCH_MODE_NONE  0x0
+#define DRV_MB_PARAM_ESWITCH_MODE_VEB   0x1
+#define DRV_MB_PARAM_ESWITCH_MODE_VEPA  0x2
+
+#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK     0x1
+#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET   0
+
 #define DRV_MB_PARAM_SET_LED_MODE_OPER         0x0
 #define DRV_MB_PARAM_SET_LED_MODE_ON           0x1
 #define DRV_MB_PARAM_SET_LED_MODE_OFF          0x2
@@ -1678,6 +1699,8 @@ struct public_drv_mb {
 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR      0x37000000
+#define FW_MSG_CODE_GET_OEM_UPDATES_DONE       0x41000000
+
 #define FW_MSG_CODE_NIG_DRAIN_DONE              0x30000000
 #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
@@ -1777,11 +1800,33 @@ struct public_drv_mb {
 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001
 /* MFW supports EEE */
 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
+/* MFW supports DRV_LOAD Timeout */
+#define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO  0x00000004
+/* MFW support complete IGU cleanup upon FLR */
+#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP        0x00000080
 /* MFW supports virtual link */
 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK       0x00010000
 
 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR  (1 << 0)
 
+#define FW_MB_PARAM_OEM_UPDATE_MASK            0xFF
+#define FW_MB_PARAM_OEM_UPDATE_OFFSET          0
+#define FW_MB_PARAM_OEM_UPDATE_BW              0x01
+#define FW_MB_PARAM_OEM_UPDATE_S_TAG           0x02
+#define FW_MB_PARAM_OEM_UPDATE_CFG             0x04
+
+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK   0x00000001
+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0
+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK   0x00000002
+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1
+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK    0x00000004
+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET  2
+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK    0x00000008
+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET  3
+
+#define FW_MB_PARAM_PPFID_BITMAP_MASK   0xFF
+#define FW_MB_PARAM_PPFID_BITMAP_OFFSET    0
+
        u32 drv_pulse_mb;
 #define DRV_PULSE_SEQ_MASK                      0x00007fff
 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000