New upstream version 17.11.5

[deb_dpdk.git] / drivers / net / virtio / virtio_pci.c

diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c
index e6da680..249ec6d 100644 (file)
--- a/drivers/net/virtio/virtio_pci.c
+++ b/drivers/net/virtio/virtio_pci.c
@@ -57,7 +57,8 @@
  * The remaining space is defined by each driver as the per-driver
  * configuration space.
  */
-#define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
+#define VIRTIO_PCI_CONFIG(hw) \
+               (((hw)->use_msix == VIRTIO_MSIX_ENABLED) ? 24 : 20)
 
 static inline int
 check_vq_phys_addr_ok(struct virtqueue *vq)
@@ -553,7 +554,7 @@ get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
        uint32_t offset = cap->offset;
        uint8_t *base;
 
-       if (bar > 5) {
+       if (bar >= PCI_MAX_RESOURCE) {
                PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
                return NULL;
        }
@@ -595,16 +596,18 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
        }
 
        ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
-       if (ret < 0) {
-               PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
+       if (ret != 1) {
+               PMD_INIT_LOG(DEBUG,
+                            "failed to read pci capability list, ret %d", ret);
                return -1;
        }
 
        while (pos) {
-               ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);
-               if (ret < 0) {
-                       PMD_INIT_LOG(ERR,
-                               "failed to read pci cap at pos: %x", pos);
+               ret = rte_pci_read_config(dev, &cap, 2, pos);
+               if (ret != 2) {
+                       PMD_INIT_LOG(DEBUG,
+                                    "failed to read pci cap at pos: %x ret %d",
+                                    pos, ret);
                        break;
                }
 
@@ -614,10 +617,21 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
                         * 1st byte is cap ID; 2nd byte is the position of next
                         * cap; next two bytes are the flags.
                         */
-                       uint16_t flags = ((uint16_t *)&cap)[1];
+                       uint16_t flags;
+
+                       ret = rte_pci_read_config(dev, &flags, sizeof(flags),
+                                       pos + 2);
+                       if (ret != sizeof(flags)) {
+                               PMD_INIT_LOG(DEBUG,
+                                            "failed to read pci cap at pos:"
+                                            " %x ret %d", pos + 2, ret);
+                               break;
+                       }
 
                        if (flags & PCI_MSIX_ENABLE)
-                               hw->use_msix = 1;
+                               hw->use_msix = VIRTIO_MSIX_ENABLED;
+                       else
+                               hw->use_msix = VIRTIO_MSIX_DISABLED;
                }
 
                if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
@@ -627,6 +641,14 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
                        goto next;
                }
 
+               ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);
+               if (ret != sizeof(cap)) {
+                       PMD_INIT_LOG(DEBUG,
+                                    "failed to read pci cap at pos: %x ret %d",
+                                    pos, ret);
+                       break;
+               }
+
                PMD_INIT_LOG(DEBUG,
                        "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
                        pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
@@ -636,9 +658,15 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
                        hw->common_cfg = get_cfg_addr(dev, &cap);
                        break;
                case VIRTIO_PCI_CAP_NOTIFY_CFG:
-                       rte_pci_read_config(dev, &hw->notify_off_multiplier,
+                       ret = rte_pci_read_config(dev,
+                                       &hw->notify_off_multiplier,
                                        4, pos + sizeof(cap));
-                       hw->notify_base = get_cfg_addr(dev, &cap);
+                       if (ret != 4)
+                               PMD_INIT_LOG(DEBUG,
+                                       "failed to read notify_off_multiplier, ret %d",
+                                       ret);
+                       else
+                               hw->notify_base = get_cfg_addr(dev, &cap);
                        break;
                case VIRTIO_PCI_CAP_DEVICE_CFG:
                        hw->dev_cfg = get_cfg_addr(dev, &cap);
@@ -710,3 +738,51 @@ vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw)
 
        return 0;
 }
+
+enum virtio_msix_status
+vtpci_msix_detect(struct rte_pci_device *dev)
+{
+       uint8_t pos;
+       int ret;
+
+       ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
+       if (ret != 1) {
+               PMD_INIT_LOG(DEBUG,
+                            "failed to read pci capability list, ret %d", ret);
+               return VIRTIO_MSIX_NONE;
+       }
+
+       while (pos) {
+               uint8_t cap[2];
+
+               ret = rte_pci_read_config(dev, cap, sizeof(cap), pos);
+               if (ret != sizeof(cap)) {
+                       PMD_INIT_LOG(DEBUG,
+                                    "failed to read pci cap at pos: %x ret %d",
+                                    pos, ret);
+                       break;
+               }
+
+               if (cap[0] == PCI_CAP_ID_MSIX) {
+                       uint16_t flags;
+
+                       ret = rte_pci_read_config(dev, &flags, sizeof(flags),
+                                       pos + sizeof(cap));
+                       if (ret != sizeof(flags)) {
+                               PMD_INIT_LOG(DEBUG,
+                                            "failed to read pci cap at pos:"
+                                            " %x ret %d", pos + 2, ret);
+                               break;
+                       }
+
+                       if (flags & PCI_MSIX_ENABLE)
+                               return VIRTIO_MSIX_ENABLED;
+                       else
+                               return VIRTIO_MSIX_DISABLED;
+               }
+
+               pos = cap[1];
+       }
+
+       return VIRTIO_MSIX_NONE;
+}