#define MIN_ZERO_POLL_COUNT 10
-/* around 100ms at 2 Ghz */
-#define TIMER_RESOLUTION_CYCLES 200000000ULL
/* 100 ms interval */
#define TIMER_NUMBER_PER_SECOND 10
/* 100000 us */
{
struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
unsigned lcore_id;
- uint64_t prev_tsc, diff_tsc, cur_tsc;
+ uint64_t prev_tsc, diff_tsc, cur_tsc, tim_res_tsc, hz;
uint64_t prev_tsc_power = 0, cur_tsc_power, diff_tsc_power;
int i, j, nb_rx;
uint8_t portid, queueid;
const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
prev_tsc = 0;
+ hz = rte_get_timer_hz();
+ tim_res_tsc = hz/TIMER_NUMBER_PER_SECOND;
lcore_id = rte_lcore_id();
qconf = &lcore_conf[lcore_id];
}
diff_tsc_power = cur_tsc_power - prev_tsc_power;
- if (diff_tsc_power > TIMER_RESOLUTION_CYCLES) {
+ if (diff_tsc_power > tim_res_tsc) {
rte_timer_manage();
prev_tsc_power = cur_tsc_power;
}
turn_on_intr(qconf);
sleep_until_rx_interrupt(
qconf->n_rx_queue);
+ /**
+ * start receiving packets immediately
+ */
+ goto start_rx;
}
- /* start receiving packets immediately */
- goto start_rx;
}
stats[lcore_id].sleep_time += lcore_idle_hint;
}