extern "C" {
#endif
+#include <stdint.h>
#include "generic/rte_atomic.h"
/**
* Guarantees that the LOAD and STORE operations generated before the
* barrier occur before the LOAD and STORE operations generated after.
*/
-#define rte_mb() {asm volatile("sync" : : : "memory"); }
+#define rte_mb() asm volatile("sync" : : : "memory")
/**
* Write memory barrier.
* occur before the STORE operations generated after.
*/
#ifdef RTE_ARCH_64
-#define rte_wmb() {asm volatile("lwsync" : : : "memory"); }
+#define rte_wmb() asm volatile("lwsync" : : : "memory")
#else
-#define rte_wmb() {asm volatile("sync" : : : "memory"); }
+#define rte_wmb() asm volatile("sync" : : : "memory")
#endif
/**
* occur before the LOAD operations generated after.
*/
#ifdef RTE_ARCH_64
-#define rte_rmb() {asm volatile("lwsync" : : : "memory"); }
+#define rte_rmb() asm volatile("lwsync" : : : "memory")
#else
-#define rte_rmb() {asm volatile("sync" : : : "memory"); }
+#define rte_rmb() asm volatile("sync" : : : "memory")
#endif
#define rte_smp_mb() rte_mb()
#define rte_smp_rmb() rte_rmb()
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
/*------------------------- 16 bit atomic operations -------------------------*/
/* To be compatible with Power7, use GCC built-in functions for 16 bit
* operations */