Merge branch 'upstream-16.11-stable' into 16.11.x

[deb_dpdk.git] / lib / librte_eal / common / include / arch / ppc_64 / rte_atomic.h

diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index feae486..790e6fd 100644 (file)
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -46,6 +46,7 @@
 extern "C" {
 #endif
 
+#include <stdint.h>
 #include "generic/rte_atomic.h"
 
 /**
@@ -54,7 +55,7 @@ extern "C" {
  * Guarantees that the LOAD and STORE operations generated before the
  * barrier occur before the LOAD and STORE operations generated after.
  */
-#define        rte_mb()  {asm volatile("sync" : : : "memory"); }
+#define        rte_mb()  asm volatile("sync" : : : "memory")
 
 /**
  * Write memory barrier.
@@ -62,7 +63,11 @@ extern "C" {
  * Guarantees that the STORE operations generated before the barrier
  * occur before the STORE operations generated after.
  */
-#define        rte_wmb() {asm volatile("sync" : : : "memory"); }
+#ifdef RTE_ARCH_64
+#define        rte_wmb() asm volatile("lwsync" : : : "memory")
+#else
+#define        rte_wmb() asm volatile("sync" : : : "memory")
+#endif
 
 /**
  * Read memory barrier.
@@ -70,13 +75,17 @@ extern "C" {
  * Guarantees that the LOAD operations generated before the barrier
  * occur before the LOAD operations generated after.
  */
-#define        rte_rmb() {asm volatile("sync" : : : "memory"); }
+#ifdef RTE_ARCH_64
+#define        rte_rmb() asm volatile("lwsync" : : : "memory")
+#else
+#define        rte_rmb() asm volatile("sync" : : : "memory")
+#endif
 
 #define rte_smp_mb() rte_mb()
 
-#define rte_smp_wmb() rte_compiler_barrier()
+#define rte_smp_wmb() rte_wmb()
 
-#define rte_smp_rmb() rte_compiler_barrier()
+#define rte_smp_rmb() rte_rmb()
 
 /*------------------------- 16 bit atomic operations -------------------------*/
 /* To be compatible with Power7, use GCC built-in functions for 16 bit