typedef struct
{
CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
- volatile u32 **lockp;
+ u8 buffer_pool_index;
+} dpdk_rx_queue_t;
- /* Instance ID to access internal device array. */
- dpdk_portid_t device_index;
+typedef struct
+{
+ CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
+ clib_spinlock_t lock;
+} dpdk_tx_queue_t;
- /* DPDK device port number */
- dpdk_portid_t port_id;
+typedef struct
+{
+ CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
+
+ dpdk_rx_queue_t *rx_queues;
+ dpdk_tx_queue_t *tx_queues;
+
+ /* Instance ID to access internal device array. */
+ u32 device_index;
u32 hw_if_index;
u32 sw_if_index;
/* next node index if we decide to steal the rx graph arc */
u32 per_interface_next_index;
+ u16 rx_q_used;
+ u16 tx_q_used;
+ u16 flags;
+
+ /* DPDK device port number */
+ dpdk_portid_t port_id;
dpdk_pmd_t pmd:8;
i8 cpu_socket;
- u16 flags;
-
- u16 nb_tx_desc;
CLIB_CACHE_LINE_ALIGN_MARK (cacheline1);
+ u16 nb_tx_desc;
+ u16 nb_rx_desc;
u8 *name;
u8 *interface_name_suffix;
u16 num_subifs;
/* PMD related */
- u16 tx_q_used;
- u16 rx_q_used;
- u16 nb_rx_desc;
- u16 *cpu_socket_id_by_queue;
- u8 *buffer_pool_for_queue;
struct rte_eth_conf port_conf;
struct rte_eth_txconf tx_conf;
#define DPDK_LINK_POLL_INTERVAL (3.0)
#define DPDK_MIN_LINK_POLL_INTERVAL (0.001) /* 1msec */
-typedef struct
-{
- u32 device;
- u16 queue_id;
-} dpdk_device_and_queue_t;
-
-#ifndef DPDK_HQOS_DBG_BYPASS
-#define DPDK_HQOS_DBG_BYPASS 0
-#endif
-
-#ifndef HQOS_FLUSH_COUNT_THRESHOLD
-#define HQOS_FLUSH_COUNT_THRESHOLD 100000
-#endif
-
-
#define foreach_dpdk_device_config_item \
_ (num_rx_queues) \
_ (num_tx_queues) \
clib_bitmap_t * workers;
u8 tso;
u8 *devargs;
+ clib_bitmap_t *rss_queues;
#define DPDK_DEVICE_TSO_DEFAULT 0
#define DPDK_DEVICE_TSO_OFF 1
void dpdk_device_setup (dpdk_device_t * xd);
void dpdk_device_start (dpdk_device_t * xd);
void dpdk_device_stop (dpdk_device_t * xd);
-
int dpdk_port_state_callback (dpdk_portid_t port_id,
enum rte_eth_event_type type,
void *param, void *ret_param);