round_pow2 (xm->n_descriptors[rt], xm->n_descriptors_per_cache_line);
dq->head_index = dq->tail_index = 0;
- dq->descriptors =
- vlib_physmem_alloc_aligned (vm, xm->physmem_region, &error,
- dq->n_descriptors *
- sizeof (dq->descriptors[0]),
- 128 /* per chip spec */ );
- if (error)
- return error;
-
- memset (dq->descriptors, 0,
- dq->n_descriptors * sizeof (dq->descriptors[0]));
+ dq->descriptors = vlib_physmem_alloc_aligned (vm, dq->n_descriptors *
+ sizeof (dq->descriptors[0]),
+ 128 /* per chip spec */ );
+ if (!dq->descriptors)
+ return vlib_physmem_last_error (vm);
+
+ clib_memset (dq->descriptors, 0,
+ dq->n_descriptors * sizeof (dq->descriptors[0]));
vec_resize (dq->descriptor_buffer_indices, dq->n_descriptors);
if (rt == VLIB_RX)
{
u32 i;
- dq->tx.head_index_write_back = vlib_physmem_alloc (vm,
- xm->physmem_region,
- &error,
- CLIB_CACHE_LINE_BYTES);
+ dq->tx.head_index_write_back =
+ vlib_physmem_alloc (vm, CLIB_CACHE_LINE_BYTES);
+ if (!dq->tx.head_index_write_back)
+ return vlib_physmem_last_error (vm);
for (i = 0; i < dq->n_descriptors; i++)
dq->descriptors[i].tx = xm->tx_descriptor_template;
ixge_dma_regs_t *dr = get_dma_regs (xd, rt, queue_index);
u64 a;
- a =
- vlib_physmem_virtual_to_physical (vm, xm->physmem_region,
- dq->descriptors);
+ a = vlib_physmem_get_pa (vm, dq->descriptors);
dr->descriptor_address[0] = a & 0xFFFFFFFF;
dr->descriptor_address[1] = a >> (u64) 32;
dr->n_descriptor_bytes = dq->n_descriptors * sizeof (dq->descriptors[0]);
/* Make sure its initialized before hardware can get to it. */
dq->tx.head_index_write_back[0] = dq->head_index;
- a = vlib_physmem_virtual_to_physical (vm, xm->physmem_region,
- dq->tx.head_index_write_back);
+ a = vlib_physmem_get_pa (vm, dq->tx.head_index_write_back);
dr->tx.head_index_write_back_address[0] = /* enable bit */ 1 | a;
dr->tx.head_index_write_back_address[1] = (u64) a >> (u64) 32;
}
vec_foreach (xd, xm->devices)
{
ixge_update_counters (xd);
- memset (xd->counters, 0, sizeof (xd->counters));
+ clib_memset (xd->counters, 0, sizeof (xd->counters));
}
timeout = 30.0;
clib_error_t *error;
xm->vlib_main = vm;
- memset (&xm->tx_descriptor_template, 0,
- sizeof (xm->tx_descriptor_template));
- memset (&xm->tx_descriptor_template_mask, 0,
- sizeof (xm->tx_descriptor_template_mask));
+ clib_memset (&xm->tx_descriptor_template, 0,
+ sizeof (xm->tx_descriptor_template));
+ clib_memset (&xm->tx_descriptor_template_mask, 0,
+ sizeof (xm->tx_descriptor_template_mask));
xm->tx_descriptor_template.status0 =
(IXGE_TX_DESCRIPTOR_STATUS0_ADVANCED |
IXGE_TX_DESCRIPTOR_STATUS0_IS_ADVANCED |
vlib_pci_addr_t *addr = vlib_pci_get_addr (vm, h);
vlib_pci_device_info_t *d = vlib_pci_get_device_info (vm, addr, 0);
- /* Allocate physmem region for DMA buffers */
- if (xm->physmem_region_allocated == 0)
- {
- error = vlib_physmem_region_alloc (vm, "ixge decriptors", 2 << 20, 0,
- VLIB_PHYSMEM_F_INIT_MHEAP,
- &xm->physmem_region);
- xm->physmem_region_allocated = 1;
- }
- if (error)
- return error;
-
error = vlib_pci_map_region (vm, h, 0, &r);
if (error)
return error;