{
memif_main_t *mm = &memif_main;
vnet_main_t *vnm = vnet_get_main ();
+ vlib_main_t *vm = vlib_get_main ();
memif_region_t *mr;
memif_queue_t *mq;
int i;
memif_log_warn (mif,
"Unable to unassign interface %d, queue %d: rc=%d",
mif->hw_if_index, i, rv);
- mq->ring = 0;
+ if (mif->flags & MEMIF_IF_FLAG_ZERO_COPY)
+ {
+
+ u16 cur_slot,last_slot, start;
+ u16 ring_size = 1 << mq->log2_ring_size;
+ u16 mask = ring_size - 1;
+ cur_slot = mq->last_tail;
+ last_slot = mq->ring->head - 1 ;
+ start = (mq->last_tail & mask);
+ u16 n_slots = ((last_slot - cur_slot) & mask) + 1;
+ vlib_buffer_free_from_ring(vm,mq->buffers,start,ring_size,n_slots);
+ }
+ mq->ring = 0;
}
}
vec_free (mif->rx_queues);
vec_foreach (mq, mif->tx_queues)
- memif_queue_intfd_close (mq);
+ {
+ if (mif->flags & MEMIF_IF_FLAG_ZERO_COPY)
+ {
+ memif_ring_t *ring = mq->ring;
+ u16 cur_slot,last_slot, start;
+ u16 ring_size = 1 << mq->log2_ring_size;
+ u16 mask = ring_size - 1;
+ u16 n_slots = ring->tail - mq->last_tail;
+ cur_slot = mq->last_tail;
+ last_slot = mq->ring->head;
+ start = (mq->last_tail & mask);
+ if(last_slot > cur_slot)
+ n_slots = n_slots + ((last_slot - cur_slot)) ;
+ else if (last_slot < cur_slot)
+ n_slots = n_slots + (cur_slot - last_slot);
+ vlib_buffer_free_from_ring_no_next (vm, mq->buffers,
+ start,
+ ring_size, n_slots);
+ }
+ memif_queue_intfd_close (mq);
+ }
+
vec_free (mif->tx_queues);
/* free memory regions */
clib_error_t *
memif_connect (memif_if_t * mif)
{
+ vlib_main_t *vm = vlib_get_main ();
vnet_main_t *vnm = vnet_get_main ();
clib_file_t template = { 0 };
memif_region_t *mr;
vec_foreach_index (i, mif->rx_queues)
{
memif_queue_t *mq = vec_elt_at_index (mif->rx_queues, i);
+ u32 ti;
int rv;
mq->ring = mif->regions[mq->region].shm + mq->offset;
memif_file_add (&mq->int_clib_file_index, &template);
}
vnet_hw_interface_assign_rx_thread (vnm, mif->hw_if_index, i, ~0);
+ ti = vnet_get_device_input_thread_index (vnm, mif->hw_if_index, i);
+ mq->buffer_pool_index =
+ vlib_buffer_pool_get_default_for_numa (vm, vlib_mains[ti]->numa_node);
rv = vnet_hw_interface_set_rx_mode (vnm, mif->hw_if_index, i,
VNET_HW_INTERFACE_RX_MODE_DEFAULT);
if (rv)
{
vlib_buffer_pool_t *bp;
/* *INDENT-OFF* */
- vec_foreach (bp, buffer_main.buffer_pools)
+ vec_foreach (bp, vm->buffer_main->buffer_pools)
{
vlib_physmem_map_t *pm;
pm = vlib_physmem_get_map (vm, bp->physmem_map_index);
/* *INDENT-OFF* */
VLIB_PLUGIN_REGISTER () = {
.version = VPP_BUILD_VER,
- .description = "Packet Memory Interface (experimental)",
+ .description = "Packet Memory Interface (memif) -- Experimental",
};
/* *INDENT-ON* */