#include <vlib/pci/pci.h>
#include <vnet/ethernet/ethernet.h>
#include <vnet/devices/devices.h>
+#include <vnet/ip/ip6_packet.h>
+#include <vnet/ip/ip4_packet.h>
#include <vmxnet3/vmxnet3.h>
vmxnet3_main_t *vmxm = &vmxnet3_main;
vnet_interface_output_runtime_t *rd = (void *) node->runtime_data;
vmxnet3_device_t *vd = pool_elt_at_index (vmxm->devices, rd->dev_instance);
- u32 *buffers = vlib_frame_args (frame);
+ u32 *buffers = vlib_frame_vector_args (frame);
u32 bi0;
vlib_buffer_t *b0;
vmxnet3_tx_desc *txd = 0;
u16 space_left;
u16 n_left = frame->n_vectors;
vmxnet3_txq_t *txq;
- u32 thread_index = vm->thread_index;
- u16 qid = thread_index;
+ u16 qid = vm->thread_index % vd->num_tx_queues, produce;
if (PREDICT_FALSE (!(vd->flags & VMXNET3_DEVICE_F_LINK_UP)))
{
return (0);
}
- txq = vec_elt_at_index (vd->txqs, qid % vd->num_tx_queues);
+ txq = vec_elt_at_index (vd->txqs, qid);
clib_spinlock_lock_if_init (&txq->lock);
vmxnet3_txq_release (vm, vd, txq);
- while (n_left)
+ produce = txq->tx_ring.produce;
+ while (PREDICT_TRUE (n_left))
{
u16 space_needed = 1, i;
+ u32 gso_size = 0;
+ u32 l4_hdr_sz;
vlib_buffer_t *b;
+ u32 hdr_len = 0;
bi0 = buffers[0];
b0 = vlib_get_buffer (vm, bi0);
txq->tx_ring.bufs[desc_idx] = bi0;
txd = &txq->tx_desc[desc_idx];
+
txd->address = vlib_buffer_get_current_pa (vm, b0);
txd->flags[0] = generation | b0->current_length;
+ txd->flags[1] = 0;
+ if (PREDICT_FALSE (b0->flags & VNET_BUFFER_F_GSO))
+ {
+ /*
+ * We should not be getting GSO outbound traffic unless it is
+ * lro is enable
+ */
+ ASSERT (vd->gso_enable == 1);
+ gso_size = vnet_buffer2 (b0)->gso_size;
+ l4_hdr_sz = vnet_buffer2 (b0)->gso_l4_hdr_sz;
+ if (b0->flags & VNET_BUFFER_F_IS_IP6)
+ hdr_len = sizeof (ethernet_header_t) + sizeof (ip6_header_t) +
+ l4_hdr_sz;
+ else
+ hdr_len = sizeof (ethernet_header_t) + sizeof (ip4_header_t) +
+ l4_hdr_sz;
+ }
generation = txq->tx_ring.gen;
-
- txd->flags[1] = 0;
bi0 = b0->next_buffer;
}
-
- txd->flags[1] = VMXNET3_TXF_CQ | VMXNET3_TXF_EOP;
+ if (PREDICT_FALSE (gso_size != 0))
+ {
+ txq->tx_desc[first_idx].flags[1] = hdr_len;
+ txq->tx_desc[first_idx].flags[1] |= VMXNET3_TXF_OM (VMXNET3_OM_TSO);
+ txq->tx_desc[first_idx].flags[0] |= VMXNET3_TXF_MSSCOF (gso_size);
+ }
+ txd->flags[1] |= VMXNET3_TXF_CQ | VMXNET3_TXF_EOP;
asm volatile ("":::"memory");
/*
* Now toggle back the generation bit for the first segment.
* Device can start reading the packet
*/
txq->tx_desc[first_idx].flags[0] ^= VMXNET3_TXF_GEN;
- vmxnet3_reg_write (vd, 0, VMXNET3_REG_TXPROD, txq->tx_ring.produce);
buffers++;
n_left--;
}
+ if (PREDICT_TRUE (produce != txq->tx_ring.produce))
+ vmxnet3_reg_write_inline (vd, 0, txq->reg_txprod, txq->tx_ring.produce);
+
clib_spinlock_unlock_if_init (&txq->lock);
return (frame->n_vectors - n_left);