#define foreach_vmxnet3_tx_func_error \
_(ERROR_PACKETS, "error packets") \
+ _(LINK_DOWN, "link down") \
_(NO_FREE_SLOTS, "no free tx slots")
typedef enum
#undef _
};
+#define foreach_vmxnet3_show_entry \
+ _(RX_COMP, "rx comp") \
+ _(RX_DESC0, "rx desc 0") \
+ _(RX_DESC1, "rx desc 1") \
+ _(TX_COMP, "tx comp") \
+ _(TX_DESC, "tx desc")
+
+enum
+{
+#define _(a, b) VMXNET3_SHOW_##a,
+ foreach_vmxnet3_show_entry
+#undef _
+};
+
+#define VMXNET3_TXQ_MAX 8
+#define VMXNET3_TX_START(vd) ((vd)->queues)
+#define VMXNET3_RX_START(vd) \
+ ((vd)->queues + (vd)->num_tx_queues * sizeof (vmxnet3_tx_queue))
+
/* BAR 0 */
#define VMXNET3_REG_IMR 0x0000 /* Interrupt Mask Register */
#define VMXNET3_REG_TXPROD 0x0600 /* Tx Producer Index */
#define VMXNET3_RXF_BTYPE (1 << 14) /* rx body buffer type */
#define VMXNET3_RXF_GEN (1 << 31) /* rx generation */
+#define VMXNET3_RXCF_IP6 (1 << 20) /* rx ip6 packet */
+#define VMXNET3_RXCF_IP4 (1 << 21) /* rx ip4 packet */
#define VMXNET3_RXCF_GEN (1 << 31) /* rx completion generation */
#define VMXNET3_RXC_INDEX (0xFFF) /* rx completion index mask */
_(7, GET_DEV_EXTRA_INFO, "get dev extra info") \
_(8, GET_CONF_INTR, "get conf intr") \
_(9, GET_ADAPTIVE_RING_INFO, "get adaptive ring info") \
- _(10, GET_TXDATA_DESC_SIZE, "gte txdata desc size") \
+ _(10, GET_TXDATA_DESC_SIZE, "get txdata desc size") \
_(11, RESERVED5, "reserved5")
enum
u8 pad[88];
}) vmxnet3_rx_queue;
-typedef CLIB_PACKED (struct
- {
- vmxnet3_tx_queue tx; vmxnet3_rx_queue rx;
- }) vmxnet3_queues;
-
/*
* flags:
* buffer length -- bits 0-13
typedef struct
{
CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
- u64 next;
u32 gen;
+ u16 next;
} vmxnet3_rx_comp_ring;
typedef struct
typedef struct
{
CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
- u64 next;
u32 gen;
+ u16 next;
} vmxnet3_tx_comp_ring;
typedef struct
{
CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
u16 size;
+ u32 reg_txprod;
clib_spinlock_t lock;
vmxnet3_tx_desc *tx_desc;
vmxnet3_tx_comp_ring tx_comp_ring;
} vmxnet3_txq_t;
-typedef CLIB_PACKED (struct
- {
- vmxnet3_queues queues; vmxnet3_shared shared;
- }) vmxnet3_dma;
-
typedef struct
{
CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
u32 dev_instance;
u32 sw_if_index;
u32 hw_if_index;
+ u32 numa_node;
vlib_pci_dev_handle_t pci_dev_handle;
vlib_pci_addr_t pci_addr;
void *bar[2];
/* error */
clib_error_t *error;
- vmxnet3_dma *dma;
+ vmxnet3_shared *driver_shared;
+ void *queues;
+ u32 link_speed;
+ vmxnet3_tx_stats *tx_stats;
+ vmxnet3_rx_stats *rx_stats;
} vmxnet3_device_t;
typedef struct
{
vmxnet3_device_t *devices;
- vlib_physmem_region_index_t physmem_region;
- u32 physmem_region_alloc;
u16 msg_id_base;
+ vlib_log_class_t log_default;
} vmxnet3_main_t;
extern vmxnet3_main_t vmxnet3_main;
u32 enable_elog;
u16 rxq_size;
u16 txq_size;
+ u16 txq_num;
/* return */
i32 rv;
u32 sw_if_index;
format_function_t format_vmxnet3_device_name;
format_function_t format_vmxnet3_input_trace;
+#define vmxnet3_log_debug(dev, f, ...) \
+ vlib_log (VLIB_LOG_LEVEL_DEBUG, vmxnet3_main.log_default, "%U: " f, \
+ format_vlib_pci_addr, &dev->pci_addr, \
+ ## __VA_ARGS__)
+
+#define vmxnet3_log_error(dev, f, ...) \
+ vlib_log (VLIB_LOG_LEVEL_ERR, vmxnet3_main.log_default, "%U: " f, \
+ format_vlib_pci_addr, &dev->pci_addr, \
+ ## __VA_ARGS__)
+
+/* no log version, called by data plane */
static_always_inline void
-vmxnet3_reg_write (vmxnet3_device_t * vd, u8 bar, u32 addr, u32 val)
+vmxnet3_reg_write_inline (vmxnet3_device_t * vd, u8 bar, u32 addr, u32 val)
{
*(volatile u32 *) ((u8 *) vd->bar[bar] + addr) = val;
}
+static_always_inline void
+vmxnet3_reg_write (vmxnet3_device_t * vd, u8 bar, u32 addr, u32 val)
+{
+ vmxnet3_log_debug (vd, "reg wr bar %u addr 0x%x val 0x%x", bar, addr, val);
+ vmxnet3_reg_write_inline (vd, bar, addr, val);
+}
+
static_always_inline u32
vmxnet3_reg_read (vmxnet3_device_t * vd, u8 bar, u32 addr)
{
- return *(volatile u32 *) (vd->bar[bar] + addr);
+ u32 val;
+
+ val = *(volatile u32 *) (vd->bar[bar] + addr);
+ vmxnet3_log_debug (vd, "reg rd bar %u addr 0x%x val 0x%x", bar, addr, val);
+
+ return val;
}
static_always_inline uword
vmxnet3_dma_addr (vlib_main_t * vm, vmxnet3_device_t * vd, void *p)
{
- vmxnet3_main_t *vmxm = &vmxnet3_main;
-
return (vd->flags & VMXNET3_DEVICE_F_IOVA) ? pointer_to_uword (p) :
- vlib_physmem_virtual_to_physical (vm, vmxm->physmem_region, p);
+ vlib_physmem_get_pa (vm, p);
}
static_always_inline void
vmxnet3_rx_desc *rxd;
u16 n_refill, n_alloc;
vmxnet3_rx_ring *ring;
+ vmxnet3_rx_queue *rx;
ring = &rxq->rx_ring[0];
n_refill = rxq->size - ring->fill;
while (n_alloc)
{
+ vlib_buffer_t *b = vlib_get_buffer (vm, ring->bufs[ring->produce]);
rxd = &rxq->rx_desc[0][ring->produce];
- rxd->address =
- vlib_get_buffer_data_physical_address (vm, ring->bufs[ring->produce]);
+ rxd->address = vlib_buffer_get_pa (vm, b);
rxd->flags = ring->gen | VLIB_BUFFER_DATA_SIZE;
vmxnet3_rx_ring_advance_produce (rxq, ring);
n_alloc--;
}
- vmxnet3_reg_write (vd, 0, VMXNET3_REG_RXPROD, ring->produce);
+ rx = VMXNET3_RX_START (vd);
+ if (PREDICT_FALSE (rx->ctrl.update_prod))
+ vmxnet3_reg_write_inline (vd, 0, VMXNET3_REG_RXPROD, ring->produce);
return 0;
}
vmxnet3_rx_desc *rxd;
u16 n_refill, n_alloc;
vmxnet3_rx_ring *ring;
+ vmxnet3_rx_queue *rx;
ring = &rxq->rx_ring[1];
n_refill = rxq->size - ring->fill;
while (n_alloc)
{
+ vlib_buffer_t *b = vlib_get_buffer (vm, ring->bufs[ring->produce]);
rxd = &rxq->rx_desc[1][ring->produce];
- rxd->address =
- vlib_get_buffer_data_physical_address (vm, ring->bufs[ring->produce]);
+ rxd->address = vlib_buffer_get_pa (vm, b);
rxd->flags = ring->gen | VLIB_BUFFER_DATA_SIZE | VMXNET3_RXF_BTYPE;
vmxnet3_rx_ring_advance_produce (rxq, ring);
n_alloc--;
}
- vmxnet3_reg_write (vd, 0, VMXNET3_REG_RXPROD2, ring->produce);
+ rx = VMXNET3_RX_START (vd);
+ if (PREDICT_FALSE (rx->ctrl.update_prod))
+ vmxnet3_reg_write_inline (vd, 0, VMXNET3_REG_RXPROD2, ring->produce);
return 0;
}
Code Review / vpp.git / blobdiff