vppinfra: refactor clib_rwlock_t to use single condition variable

[vpp.git] / src / vppinfra / cache.h

diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index 7a54d34..e2c406d 100644 (file)
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -58,6 +58,12 @@
 
 #define CLIB_CACHE_LINE_BYTES (1 << CLIB_LOG2_CACHE_LINE_BYTES)
 #define CLIB_CACHE_LINE_ALIGN_MARK(mark) u8 mark[0] __attribute__((aligned(CLIB_CACHE_LINE_BYTES)))
+#define CLIB_CACHE_LINE_ROUND(x) ((x + CLIB_CACHE_LINE_BYTES - 1) & ~(CLIB_CACHE_LINE_BYTES - 1))
+
+/* Default cache line fill buffers. */
+#ifndef CLIB_N_PREFETCHES
+#define CLIB_N_PREFETCHES 16
+#endif
 
 /* Read/write arguments to __builtin_prefetch. */
 #define CLIB_PREFETCH_READ 0