Support dynamic dual/quad loop selection on aarch64

[vpp.git] / src / vppinfra / cache.h

diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index ac08355..e8e89ba 100644 (file)
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -45,9 +45,6 @@
  */
 #ifndef CLIB_LOG2_CACHE_LINE_BYTES
 
-/* defines CLIB_LOG2_CACHE_LINE_BYTES */
-#include <vppinfra/config.h>
-
 /* Default cache line size of 64 bytes. */
 #ifndef CLIB_LOG2_CACHE_LINE_BYTES
 #define CLIB_LOG2_CACHE_LINE_BYTES 6
@@ -62,6 +59,11 @@
 #define CLIB_CACHE_LINE_BYTES (1 << CLIB_LOG2_CACHE_LINE_BYTES)
 #define CLIB_CACHE_LINE_ALIGN_MARK(mark) u8 mark[0] __attribute__((aligned(CLIB_CACHE_LINE_BYTES)))
 
+/* Default cache line fill buffers. */
+#ifndef CLIB_N_PREFETCHES
+#define CLIB_N_PREFETCHES 16
+#endif
+
 /* Read/write arguments to __builtin_prefetch. */
 #define CLIB_PREFETCH_READ 0
 #define CLIB_PREFETCH_LOAD 0   /* alias for read */