ikev2: add support for custom ipsec-over-udp port

[vpp.git] / src / vppinfra / clib.h

diff --git a/src/vppinfra/clib.h b/src/vppinfra/clib.h
index 42748b0..dac41ad 100644 (file)
--- a/src/vppinfra/clib.h
+++ b/src/vppinfra/clib.h
@@ -38,12 +38,15 @@
 #ifndef included_clib_h
 #define included_clib_h
 
+#include <vppinfra/config.h>
+
 /* Standalone means to not assume we are running on a Unix box. */
 #if ! defined (CLIB_STANDALONE) && ! defined (CLIB_LINUX_KERNEL)
 #define CLIB_UNIX
 #endif
 
 #include <vppinfra/types.h>
+#include <vppinfra/atomics.h>
 
 /* Global DEBUG flag.  Setting this to 1 or 0 turns off
    ASSERT (see vppinfra/error.h) & other debugging code. */
@@ -78,6 +81,9 @@
 #define CLIB_PACKED(x) x __attribute__ ((packed))
 #define CLIB_UNUSED(x) x __attribute__ ((unused))
 
+/* similar to CLIB_CACHE_LINE_ALIGN_MARK() but with arbitrary alignment */
+#define CLIB_ALIGN_MARK(name, alignment) u8 name[0] __attribute__((aligned(alignment)))
+
 /* Make a string from the macro's argument */
 #define CLIB_STRING_MACRO(x) #x
 
@@ -105,6 +111,14 @@
 #define PREDICT_FALSE(x) __builtin_expect((x),0)
 #define PREDICT_TRUE(x) __builtin_expect((x),1)
 
+/*
+ * Compiler barrier
+ *   prevent compiler to reorder memory access accross this boundary
+ *   prevent compiler to cache values in register (force reload)
+ * Not to be confused with CPU memory barrier below
+ */
+#define CLIB_COMPILER_BARRIER() asm volatile ("":::"memory")
+
 /* Full memory barrier (read and write). */
 #define CLIB_MEMORY_BARRIER() __sync_synchronize ()