uword * coremask;
} vlib_thread_registration_t;
-#define VLIB_MAX_CPUS 32
-
-/*
- * Objects passed around by "index" are cache-line aligned.
- * We can stick the owner CPU into the low 6 bits.
+/*
+ * Frames have their cpu / vlib_main_t index in the low-order N bits
+ * Make VLIB_MAX_CPUS a power-of-two, please...
*/
-#if VLIB_MAX_CPUS > 64
-#error VLIB_MAX_CPUS must be <= 64
+
+#ifndef VLIB_MAX_CPUS
+#define VLIB_MAX_CPUS 256
+#endif
+
+#if VLIB_MAX_CPUS > CLIB_MAX_MHEAPS
+#error Please increase number of per-cpu mheaps
#endif
#define VLIB_CPU_MASK (VLIB_MAX_CPUS - 1) /* 0x3f, max */
u32 instance_id;
vlib_thread_registration_t *registration;
u8 *name;
+ u64 barrier_sync_count;
long lwp;
int dpdk_lcore_id;