Add support for multiple microarchitectures in single binary

[vpp.git] / vnet / vnet / mpls-gre / policy_encap.c

diff --git a/vnet/vnet/mpls-gre/policy_encap.c b/vnet/vnet/mpls-gre/policy_encap.c
index 5341151..e3f4beb 100644 (file)
--- a/vnet/vnet/mpls-gre/policy_encap.c
+++ b/vnet/vnet/mpls-gre/policy_encap.c
@@ -109,7 +109,7 @@ mpls_policy_encap (vlib_main_t * vm,
 
           vlib_buffer_advance (b0, -(word)vec_len(e0->rewrite));
           h0 = vlib_buffer_get_current (b0);
-          memcpy (h0, e0->rewrite, vec_len(e0->rewrite));
+          clib_memcpy (h0, e0->rewrite, vec_len(e0->rewrite));
 
           next0 = e0->output_next_index;
 
@@ -153,11 +153,14 @@ VLIB_REGISTER_NODE (mpls_policy_encap_node) =  {
   },
 };
 
+VLIB_NODE_FUNCTION_MULTIARCH (mpls_policy_encap_node, mpls_policy_encap)
+
 static clib_error_t *
 mpls_policy_encap_init (vlib_main_t * vm)
 {
   mpls_main_t * mm = &mpls_main;
   clib_error_t * error;
+  u32 ip6_next_index;
 
   if ((error = vlib_call_init_function (vm, mpls_init)))
     return error;
@@ -166,6 +169,21 @@ mpls_policy_encap_init (vlib_main_t * vm)
     vlib_node_add_next (mm->vlib_main,
                         ip4_classify_node.index, 
                         mpls_policy_encap_node.index);
+
+  /* 
+   * Must add the same arc to ip6_classify so the
+   * next-index vectors are congruent
+   */
+  ip6_next_index = 
+    vlib_node_add_next (mm->vlib_main,
+                        ip6_classify_node.index, 
+                        mpls_policy_encap_node.index);
+
+  if (ip6_next_index != mm->ip_classify_mpls_policy_encap_next_index)
+    return clib_error_return 
+      (0, "ip4/ip6 classifier next vector botch: %d vs %d", 
+       ip6_next_index, mm->ip_classify_mpls_policy_encap_next_index);
+
   return 0;
 }