X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;ds=sidebyside;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fvts.rst;h=305a22baa972b1c784cdc86d60a7ae780caf3817;hb=bc62be08dd974d6efa960673e5d4c16402071750;hp=fbc6a41d29c069647e101e4e5088b08845b63f87;hpb=5a2c06dc4e1d3395082b6afef657453cb5bab18d;p=csit.git diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst index fbc6a41d29..305a22baa9 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst @@ -3,8 +3,8 @@ \clearpage -VTS -=== +Virtual Topology System +======================= This section includes summary graphs of VPP Phy-to-VM(s)-to-Phy packet latency with with VM virtio and VPP vhost-user virtual interfaces @@ -14,61 +14,8 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository `_. +`CSIT git repository `_. -3n-hsw-x520 -~~~~~~~~~~~ +.. toctree:: -114b-1t1c ---------- -.. raw:: html - -
- -:index:`Latency: vts-3n-hsw-x520-114b-1t1c-ndr` - -.. raw:: html - - - -



-
- -.. raw:: latex - - \begin{figure}[H] - \centering - \graphicspath{{../_build/_static/vpp/}} - \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{vts-3n-hsw-x520-114b-1t1c-ndr-lat} - \label{fig:vts-3n-hsw-x520-114b-1t1c-ndr-lat} - \end{figure} - -.. raw:: latex - - \clearpage - -114b-2t2c ---------- - -.. raw:: html - -
- -:index:`Latency: vts-3n-hsw-x520-114b-2t2c-ndr` - -.. raw:: html - - - -



-
- -.. raw:: latex - - \begin{figure}[H] - \centering - \graphicspath{{../_build/_static/vpp/}} - \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{vts-3n-hsw-x520-114b-2t2c-ndr-lat} - \label{fig:vts-3n-hsw-x520-114b-2t2c-ndr-lat} - \end{figure}