X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Fvnet%2Fadj%2Fadj_l2.c;h=09bf468ac40b212690dd783e455c5de911df459b;hb=609e121;hp=5a08364330284dee0a5477e181c0474aca2c3b74;hpb=044183faacc5eb8a055658f9deebefb56b254adc;p=vpp.git

diff --git a/src/vnet/adj/adj_l2.c b/src/vnet/adj/adj_l2.c
index 5a083643302..09bf468ac40 100644
--- a/src/vnet/adj/adj_l2.c
+++ b/src/vnet/adj/adj_l2.c
@@ -52,7 +52,7 @@ adj_l2_rewrite_inline (vlib_main_t * vm,
 {
     u32 * from = vlib_frame_vector_args (frame);
     u32 n_left_from, n_left_to_next, * to_next, next_index;
-    u32 cpu_index = os_get_cpu_number();
+    u32 thread_index = vlib_get_thread_index();
     ethernet_main_t * em = &ethernet_main;
 
     n_left_from = frame->n_vectors;
@@ -81,9 +81,6 @@ adj_l2_rewrite_inline (vlib_main_t * vm,
 
 	    adj_index0 = vnet_buffer (p0)->ip.adj_index[VLIB_TX];
 
-	    /* We should never rewrite a pkt using the MISS adjacency */
-	    ASSERT(adj_index0);
-
 	    adj0 = adj_get (adj_index0);
 
 	    /* Guess we are only writing on simple Ethernet header. */
@@ -93,9 +90,15 @@ adj_l2_rewrite_inline (vlib_main_t * vm,
 	    /* Update packet buffer attributes/set output interface. */
 	    rw_len0 = adj0[0].rewrite_header.data_bytes;
 	    vnet_buffer(p0)->ip.save_rewrite_length = rw_len0;
+            vnet_buffer(p0)->sw_if_index[VLIB_TX] = adj0->rewrite_header.sw_if_index;
+            /* since we are coming out of the L2 world, where the vlib_buffer
+             * union is used for other things, make sure it is clean for
+             * MPLS from now on.
+             */
+            vnet_buffer(p0)->mpls.first = 0;
 
 	    vlib_increment_combined_counter(&adjacency_counters,
-                                            cpu_index,
+                                            thread_index,
                                             adj_index0,
                                             /* packet increment */ 0,
                                             /* byte increment */ rw_len0);
@@ -112,7 +115,9 @@ adj_l2_rewrite_inline (vlib_main_t * vm,
 
 		if (is_midchain)
 		{
-		    adj0->sub_type.midchain.fixup_func(vm, adj0, p0);
+		    adj0->sub_type.midchain.fixup_func(
+                        vm, adj0, p0,
+                        adj0->sub_type.midchain.fixup_data);
 		}
 
 		vnet_buffer (p0)->sw_if_index[VLIB_TX] = tx_sw_if_index0;