X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Fphysical_testbeds.rst;h=5a9b1edf97158826dbb84f1f4e6f679777dccee7;hb=4ad8883c4faaa8cf519fc991068716a523f4cd5a;hp=2497de88b954a3889cf164556da4af587a534799;hpb=14fe52e81c59a5a3558f4f587e56b75e388191dc;p=csit.git

diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst
index 2497de88b9..5a9b1edf97 100644
--- a/docs/report/introduction/physical_testbeds.rst
+++ b/docs/report/introduction/physical_testbeds.rst
@@ -241,88 +241,6 @@ SUT and TG NICs:
 All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
 doubling the number of logical cores exposed to Linux.
 
-.. _physical_testbeds_2n_dnv:
-
-2-Node Atom Denverton (2n-dnv)
-------------------------------
-
-2n-dnv testbed is built with: i) one Intel S2600WFT server acting as TG
-and equipped with two Intel Xeon Skylake Platinum 8180 processors (38.5
-MB Cache, 2.50 GHz, 28 cores), and ii) one SuperMicro SYS-E300-9A server
-acting as SUT and equipped with one Intel Atom C3858 processor (12 MB
-Cache, 2.00 GHz, 12 cores). 2n-dnv physical topology is shown below.
-
-.. only:: latex
-
-    .. raw:: latex
-
-        \begin{figure}[H]
-            \centering
-                \graphicspath{{../_tmp/src/introduction/}}
-                \includegraphics[width=0.90\textwidth]{testbed-2n-dnv}
-                \label{fig:testbed-2n-dnv}
-        \end{figure}
-
-.. only:: html
-
-    .. figure:: testbed-2n-dnv.svg
-        :alt: testbed-2n-dnv
-        :align: center
-
-SUT 10GE NIC ports:
-
-#. P-1: x553 copper port.
-#. P-2: x553 copper port.
-#. P-3: x553 fiber port.
-#. P-4: x553 fiber port.
-
-TG NICs:
-
-#. NIC-1: x550-T2 2p10GE Intel.
-#. NIC-2: x550-T2 2p10GE Intel.
-#. NIC-3: x520-DA2 2p10GE Intel.
-#. NIC-4: x520-DA2 2p10GE Intel.
-
-The 2n-dnv testbed is in operation in Intel SH labs.
-
-.. _physical_testbeds_3n_dnv:
-
-3-Node Atom Denverton (3n-dnv)
-------------------------------
-
-One 3n-dnv testbed is built with: i) one SuperMicro SYS-7049GP-TRT
-server acting as TG and equipped with two Intel Xeon Skylake Platinum
-8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one
-SuperMicro SYS-E300-9A server acting as SUT and equipped with one Intel
-Atom C3858 processor (12 MB Cache, 2.00 GHz, 12 cores). 3n-dnv physical
-topology is shown below.
-
-.. only:: latex
-
-    .. raw:: latex
-
-        \begin{figure}[H]
-            \centering
-                \graphicspath{{../_tmp/src/introduction/}}
-                \includegraphics[width=0.90\textwidth]{testbed-3n-dnv}
-                \label{fig:testbed-3n-dnv}
-        \end{figure}
-
-.. only:: html
-
-    .. figure:: testbed-3n-dnv.svg
-        :alt: testbed-3n-dnv
-        :align: center
-
-SUT1 and SUT2 NICs:
-
-#. NIC-1: x553 2p10GE fiber Intel.
-#. NIC-2: x553 2p10GE copper Intel.
-
-TG NICs:
-
-#. NIC-1: x710-DA4 4p10GE Intel.
-
 .. _physical_testbeds_3n_alt:
 
 3-Node ARM Altra (3n-alt)