X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=docs%2Freport%2Fintroduction%2Ftest_environment_intro.rst;h=10ba083a12f5d098792a4631a8028e8075b7a104;hb=refs%2Fchanges%2F52%2F36652%2F3;hp=4f645713aab23ebcc83e441ee11469d0a8930c93;hpb=f82f4fdc96cfc3c1891deb4b1afb49b7746f041c;p=csit.git

diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst
index 4f645713aa..10ba083a12 100644
--- a/docs/report/introduction/test_environment_intro.rst
+++ b/docs/report/introduction/test_environment_intro.rst
@@ -13,6 +13,9 @@ Any benchmark anomalies (progressions, regressions) between releases of
 a DUT application (e.g. VPP, DPDK), are determined by testing it in the
 same test environment, to avoid test environment changes clouding the
 picture.
+To beter distinguish impact of test environment changes,
+we also execute tests without any SUT (just with TRex TG sending packets
+over a link looping back to TG).
 
 A mirror approach is introduced to determine benchmarking anomalies due
 to the test environment change. This is achieved by testing the same DUT
@@ -32,12 +35,12 @@ included in the CSIT environment versioning include:
   <https://git.fd.io/csit/tree/docs/lab/testbeds_sm_skx_hw_bios_cfg.md#n556>`_.
 - **Linux** Server Linux OS version and configuration, tracked in CSIT
   Reports in `SUT Settings
-  <https://docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_
+  <https://s3-docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_
   and `Pre-Test Server Calibration
-  <https://docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#pre-test-server-calibration>`_.
+  <https://s3-docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#id21>`_.
 - **TRex** TRex Traffic Generator version, drivers and configuration
   tracked in `TG Settings
-  <https://docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_.
+  <https://s3-docs.fd.io/csit/master/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_.
 - **CSIT** CSIT framework code tracked in CSIT release branches.
 
 Following is the list of CSIT versions to date:
@@ -70,41 +73,54 @@ Following is the list of CSIT versions to date:
   - The main change is TRex data-plane core resource adjustments:
     `increase from 7 to 8 cores and pinning cores to interfaces <https://gerrit.fd.io/r/c/csit/+/28184>`_
     for better TRex performance with symmetric traffic profiles.
-
-
-To identify performance changes due to VPP code development from
-v20.05.0 to v20.09.0, both have been tested in CSIT environment ver. 5
-and compared against each other. All substantial progressions and
-regressions have been marked up with RCA analysis. See
-:ref:`vpp_throughput_comparisons` and :ref:`vpp_known_issues`.
-
-CSIT environment ver. 5 has been evaluated against the ver. 4 by
-benchmarking VPP v20.05.0 in both environment versions.
-
-Physical Testbeds
------------------
-
-FD.io CSIT performance tests are executed in physical testbeds hosted by
-:abbr:`LF (Linux Foundation)` for FD.io project. Two physical testbed
-topology types are used:
-
-- **3-Node Topology**: Consisting of two servers acting as SUTs
-  (Systems Under Test) and one server as TG (Traffic Generator), all
-  connected in ring topology.
-- **2-Node Topology**: Consisting of one server acting as SUTs and one
-  server as TG both connected in ring topology.
-
-Tested SUT servers are based on a range of processors including Intel
-Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm,
-Intel Atom. More detailed description is provided in
-:ref:`tested_physical_topologies`. Tested logical topologies are
-described in :ref:`tested_logical_topologies`.
-
-Server Specifications
----------------------
-
-Complete technical specifications of compute servers used in CSIT
-physical testbeds are maintained in FD.io CSIT repository:
-`FD.io CSIT testbeds - Xeon Cascade Lake`_,
-`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and
-`FD.io CSIT Testbeds - Xeon Haswell`_.
+- Ver. 6 associated with CSIT rls2101 branch (`HW
+  <https://git.fd.io/csit/tree/docs/lab?h=rls2101>`_, `Linux
+  <https://docs.fd.io/csit/rls2101/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_,
+  `TRex
+  <https://docs.fd.io/csit/rls2101/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_,
+  `CSIT <https://git.fd.io/csit/tree/?h=rls2101>`_).
+
+  - The main change is TRex version upgrade:
+    `increase from 2.82 to 2.86 <https://gerrit.fd.io/r/c/csit/+/29980>`_.
+- Ver. 7 associated with CSIT rls2106 branch (`HW
+  <https://git.fd.io/csit/tree/docs/lab?h=rls2106>`_, `Linux
+  <https://s3-docs.fd.io/csit/rls2106/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_,
+  `TRex
+  <https://s3-docs.fd.io/csit/rls2106/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_,
+  `CSIT <https://git.fd.io/csit/tree/?h=rls2106>`_).
+
+  - TRex version upgrade:
+    `increase from 2.86 to 2.88 <https://gerrit.fd.io/r/c/csit/+/31652>`_.
+  - Ubuntu upgrade:
+    `upgrade from 18.04 LTS to 20.04.2 LTS <https://gerrit.fd.io/r/c/csit/+/31290>`_.
+- Ver. 8 associated with CSIT rls2110 branch (`HW
+  <https://git.fd.io/csit/tree/docs/lab?h=rls2110>`_, `Linux
+  <https://s3-docs.fd.io/csit/rls2110/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_,
+  `TRex
+  <https://s3-docs.fd.io/csit/rls2110/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_,
+  `CSIT <https://git.fd.io/csit/tree/?h=rls2110>`_).
+
+  - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility
+    matrix.
+- Ver. 9 associated with CSIT rls2202 branch (`HW
+  <https://git.fd.io/csit/tree/docs/lab?h=rls2202>`_, `Linux
+  <https://s3-docs.fd.io/csit/rls2202/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_,
+  `TRex
+  <https://s3-docs.fd.io/csit/rls2202/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_,
+  `CSIT <https://git.fd.io/csit/tree/?h=rls2202>`_).
+
+  - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility
+    matrix.
+- Ver. 10 associated with CSIT rls2206 branch (`HW
+  <https://git.fd.io/csit/tree/docs/lab?h=rls2206>`_, `Linux
+  <https://s3-docs.fd.io/csit/rls2206/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_,
+  `TRex
+  <https://s3-docs.fd.io/csit/rls2206/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_,
+  `CSIT <https://git.fd.io/csit/tree/?h=rls2206>`_).
+
+  - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility
+    matrix.
+  - Mellanox 556A series firmware upgrade based on DPDK compatibility
+    matrix.
+  - Intel IceLake all core turbo frequency turned off. Current base frequency
+    is 2.6GHz.
\ No newline at end of file