X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fhdrh_packet_latency_graphs%2Fl2.rst;h=8f8d058eb5e8ad04b40b555b5e4037e561742c9b;hb=8da14b3b1d12f48a405ad23cf8ef49a3f6d26b1e;hp=9643740888b9921bdbfe543f3cbf7746f59cf189;hpb=174ad309b359e9b323b97cae0a6877dce33deb5f;p=csit.git diff --git a/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/l2.rst index 9643740888..8f8d058eb5 100644 --- a/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/l2.rst +++ b/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/l2.rst @@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository `_. +`CSIT git repository `_. .. toctree:: @@ -21,5 +21,8 @@ CSIT source code for the test cases used for plots can be found in l2-2n-skx-x710 l2-3n-skx-xxv710 l2-3n-skx-x710 + l2-2n-clx-xxv710 + l2-2n-clx-x710 + l2-2n-clx-cx556a l2-3n-hsw-xl710 l2-3n-tsh-x520