X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fl2.rst;h=8f8d058eb5e8ad04b40b555b5e4037e561742c9b;hb=8da14b3b1d12f48a405ad23cf8ef49a3f6d26b1e;hp=3aae134c624348487e4262db479a0be3679f17da;hpb=dfff0ee80f3912a6db3f4356254f4cb3e3a9450d;p=csit.git
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
index 3aae134c62..8f8d058eb5 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
@@ -1,34 +1,8 @@
-
.. raw:: latex
\clearpage
-.. raw:: html
-
-
-
L2 Ethernet Switching
=====================
@@ -39,14 +13,16 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository `_.
+`CSIT git repository `_.
.. toctree::
- l2-3n-hsw-x520
- l2-3n-hsw-x710
- l2-3n-hsw-xl710
- l2-3n-skx-x710
- l2-3n-skx-xxv710
- l2-2n-skx-x710
l2-2n-skx-xxv710
+ l2-2n-skx-x710
+ l2-3n-skx-xxv710
+ l2-3n-skx-x710
+ l2-2n-clx-xxv710
+ l2-2n-clx-x710
+ l2-2n-clx-cx556a
+ l2-3n-hsw-xl710
+ l2-3n-tsh-x520