X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fl2.rst;h=9643740888b9921bdbfe543f3cbf7746f59cf189;hb=99219815466588419bd6705ff2ad8a9d9fc90dff;hp=642f995ccb10a74d338dca52b5a15b6aaf9a400a;hpb=53310a9c512daecbe20a45eb48f5167ea5a6a8b2;p=csit.git
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
index 642f995ccb..9643740888 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
@@ -1,34 +1,8 @@
-
.. raw:: latex
\clearpage
-.. raw:: html
-
-
-
L2 Ethernet Switching
=====================
@@ -39,14 +13,13 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository `_.
+`CSIT git repository `_.
.. toctree::
- l2-3n-hsw-x520
- l2-3n-hsw-x710
- l2-3n-hsw-xl710
- l2-3n-skx-x710
- l2-3n-skx-xxv710
- l2-2n-skx-x710
l2-2n-skx-xxv710
+ l2-2n-skx-x710
+ l2-3n-skx-xxv710
+ l2-3n-skx-x710
+ l2-3n-hsw-xl710
+ l2-3n-tsh-x520