X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fvts.rst;h=305a22baa972b1c784cdc86d60a7ae780caf3817;hb=89d1c95ef55a732f1d5dfbbb8a2117439ac05bd4;hp=5a5a9a64d2c28a98ec41458bfc65940928b1c081;hpb=53310a9c512daecbe20a45eb48f5167ea5a6a8b2;p=csit.git

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
index 5a5a9a64d2..305a22baa9 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
@@ -3,8 +3,8 @@
 
     \clearpage
 
-VTS
-===
+Virtual Topology System
+=======================
 
 This section includes summary graphs of VPP Phy-to-VM(s)-to-Phy packet
 latency with with VM virtio and VPP vhost-user virtual interfaces
@@ -14,8 +14,8 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s)
 placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1901>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1908>`_.
 
 .. toctree::
 
-    vts-3n-hsw-x520
+