X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=docs%2Freport%2Fvpp_performance_tests%2Fpacket_latency_graphs%2Fvts.rst;h=5a5a9a64d2c28a98ec41458bfc65940928b1c081;hb=53f44d52b513fae893e7774d77e3cff160ed9abe;hp=cc114bb8dc2b391fb33890dde3e85299aa429bbb;hpb=8243ea78854683f2f80da53d8f197f10316e4801;p=csit.git
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
index cc114bb8dc..5a5a9a64d2 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/vts.rst
@@ -3,31 +3,6 @@
\clearpage
-.. raw:: html
-
-
-
VTS
===
@@ -39,61 +14,8 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s)
placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository `_.
-
-3n-hsw-x520
-~~~~~~~~~~~
-
-114b-1t1c
----------
-
-.. raw:: html
-
-
-
-:index:`Packet Latency: vts-3n-hsw-x520-114b-1t1c-ndr`
-
-.. raw:: html
-
-
-
-
-
-
-.. raw:: latex
-
- \begin{figure}[H]
- \centering
- \graphicspath{{../_build/_static/vpp/}}
- \includegraphics[clip, trim=0cm 0cm 5cm 0cm, width=0.70\textwidth]{vts-3n-hsw-x520-114b-1t1c-ndr-lat}
- \label{fig:vts-3n-hsw-x520-114b-1t1c-ndr-lat}
- \end{figure}
-
-.. raw:: latex
-
- \clearpage
-
-114b-2t2c
----------
+`CSIT git repository `_.
-.. raw:: html
-
-
-
-:index:`Packet Latency: vts-3n-hsw-x520-114b-2t2c-ndr`
-
-.. raw:: html
-
-
-
-
-
-
-.. raw:: latex
+.. toctree::
- \begin{figure}[H]
- \centering
- \graphicspath{{../_build/_static/vpp/}}
- \includegraphics[clip, trim=0cm 0cm 5cm 0cm, width=0.70\textwidth]{vts-3n-hsw-x520-114b-2t2c-ndr-lat}
- \label{fig:vts-3n-hsw-x520-114b-2t2c-ndr-lat}
- \end{figure}
+ vts-3n-hsw-x520