X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2x%2Fbnx2x.h;h=c93f148bf4f944be1229ea3873e62a508bc54854;hb=6e7cbd63706f3435b9d9a2057a37db1da01db9a7;hp=5cefea4364064f4423458a7876130064b35e6bfa;hpb=6b3e017e5d25f15da73f7700f7f2ac553ef1a2e9;p=deb_dpdk.git diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 5cefea43..c93f148b 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -18,6 +18,8 @@ #include #include +#include +#include #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN #ifndef __LITTLE_ENDIAN @@ -316,7 +318,7 @@ struct bnx2x_bar { /* Used to manage DMA allocations. */ struct bnx2x_dma { struct bnx2x_softc *sc; - phys_addr_t paddr; + rte_iova_t paddr; void *vaddr; int nseg; char msg[RTE_MEMZONE_NAMESIZE - 6]; @@ -369,10 +371,10 @@ struct bnx2x_fastpath { struct bnx2x_dma sb_dma; union bnx2x_host_hc_status_block status_block; - phys_addr_t tx_desc_mapping; + rte_iova_t tx_desc_mapping; - phys_addr_t rx_desc_mapping; - phys_addr_t rx_comp_mapping; + rte_iova_t rx_desc_mapping; + rte_iova_t rx_comp_mapping; uint16_t *sb_index_values; uint16_t *sb_running_index; @@ -467,7 +469,7 @@ union cdu_context { struct hw_context { struct bnx2x_dma vcxt_dma; union cdu_context *vcxt; - //phys_addr_t cxt_mapping; + //rte_iova_t cxt_mapping; size_t size; }; @@ -1146,11 +1148,12 @@ struct bnx2x_softc { #define BNX2X_RECOVERY_NIC_LOADING 5 uint32_t rx_mode; -#define BNX2X_RX_MODE_NONE 0 -#define BNX2X_RX_MODE_NORMAL 1 -#define BNX2X_RX_MODE_ALLMULTI 2 -#define BNX2X_RX_MODE_PROMISC 3 -#define BNX2X_MAX_MULTICAST 64 +#define BNX2X_RX_MODE_NONE 0 +#define BNX2X_RX_MODE_NORMAL 1 +#define BNX2X_RX_MODE_ALLMULTI 2 +#define BNX2X_RX_MODE_ALLMULTI_PROMISC 3 +#define BNX2X_RX_MODE_PROMISC 4 +#define BNX2X_MAX_MULTICAST 64 struct bnx2x_port port; @@ -1240,7 +1243,7 @@ struct bnx2x_softc { uint32_t gz_outlen; #define GUNZIP_BUF(sc) (sc->gz_buf) #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) -#define GUNZIP_PHYS(sc) (phys_addr_t)(sc->gz_buf_dma.paddr) +#define GUNZIP_PHYS(sc) (rte_iova_t)(sc->gz_buf_dma.paddr) #define FW_BUF_SIZE 0x40000 struct raw_op *init_ops; @@ -1308,14 +1311,14 @@ struct bnx2x_softc { */ int fw_stats_req_size; struct bnx2x_fw_stats_req *fw_stats_req; - phys_addr_t fw_stats_req_mapping; + rte_iova_t fw_stats_req_mapping; /* * FW statistics data shortcut (points at the beginning of fw_stats * buffer + fw_stats_req_size). */ int fw_stats_data_size; struct bnx2x_fw_stats_data *fw_stats_data; - phys_addr_t fw_stats_data_mapping; + rte_iova_t fw_stats_data_mapping; /* tracking a pending STAT_QUERY ramrod */ uint16_t stats_pending; @@ -1400,8 +1403,8 @@ union bnx2x_stats_show_data { #define FUNC_FLG_LEADING 0x0020 /* PF only */ struct bnx2x_func_init_params { - phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ - phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ + rte_iova_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ + rte_iova_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ uint16_t func_flgs; uint16_t func_id; /* abs function id */ uint16_t pf_id; @@ -1419,8 +1422,7 @@ bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) { PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); - *((volatile uint8_t*) - ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; + rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); } static inline void @@ -1433,8 +1435,8 @@ bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) #endif PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x", (unsigned long)offset, val); - *((volatile uint16_t*) - ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; + rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); + } static inline void @@ -1448,8 +1450,7 @@ bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); - *((volatile uint32_t*) - ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; + rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); } static inline uint8_t @@ -1457,8 +1458,7 @@ bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) { uint8_t val; - val = (uint8_t)(*((volatile uint8_t*) - ((uintptr_t)sc->bar[BAR0].base_addr + offset))); + val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset); PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); @@ -1476,8 +1476,7 @@ bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) (unsigned long)offset); #endif - val = (uint16_t)(*((volatile uint16_t*) - ((uintptr_t)sc->bar[BAR0].base_addr + offset))); + val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset)); PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); @@ -1495,8 +1494,7 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) (unsigned long)offset); #endif - val = (uint32_t)(*((volatile uint32_t*) - ((uintptr_t)sc->bar[BAR0].base_addr + offset))); + val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset)); PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); @@ -1528,12 +1526,12 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) #define REG_RD_DMAE(sc, offset, valp, len32) \ do { \ (void)bnx2x_read_dmae(sc, offset, len32); \ - (void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \ + rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \ } while (0) #define REG_WR_DMAE(sc, offset, valp, len32) \ do { \ - (void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \ + rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \ (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \ } while (0) @@ -1560,11 +1558,9 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) #define DPM_TRIGGER_TYPE 0x40 /* Doorbell macro */ -#define BNX2X_DB_WRITE(db_bar, val) \ - *((volatile uint32_t *)(db_bar)) = (val) +#define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar)) -#define BNX2X_DB_READ(db_bar) \ - *((volatile uint32_t *)(db_bar)) +#define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar) #define DOORBELL_ADDR(sc, offset) \ (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset))) @@ -1753,7 +1749,7 @@ uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type, uint8_t comp_type); void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx); void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32); -void bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, +void bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr, uint32_t len32); void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt, uint32_t cid); @@ -1934,6 +1930,7 @@ void bnx2x_link_status_update(struct bnx2x_softc *sc); int bnx2x_complete_sp(struct bnx2x_softc *sc); int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc); void bnx2x_periodic_callout(struct bnx2x_softc *sc); +void bnx2x_periodic_stop(void *param); int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count); void bnx2x_vf_close(struct bnx2x_softc *sc); @@ -1982,7 +1979,7 @@ bnx2x_set_rx_mode(struct bnx2x_softc *sc) static inline int pci_read(struct bnx2x_softc *sc, size_t addr, void *val, uint8_t size) { - if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) { + if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) { PMD_DRV_LOG(ERR, "Can't read from PCI config space"); return ENXIO; } @@ -1994,7 +1991,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val) { uint16_t val16 = val; - if (rte_eal_pci_write_config(sc->pci_dev, &val16, + if (rte_pci_write_config(sc->pci_dev, &val16, sizeof(val16), addr) <= 0) { PMD_DRV_LOG(ERR, "Can't write to PCI config space"); return ENXIO; @@ -2006,7 +2003,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val) static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val) { uint32_t val32 = val; - if (rte_eal_pci_write_config(sc->pci_dev, &val32, + if (rte_pci_write_config(sc->pci_dev, &val32, sizeof(val32), addr) <= 0) { PMD_DRV_LOG(ERR, "Can't write to PCI config space"); return ENXIO;