X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=drivers%2Fnet%2Fqede%2Fbase%2Fmcp_public.h;h=8070d28d980b6a65f34aa5b713cbc80b24e9908b;hb=597cb1874068054d4c0be41f161a72ef37888930;hp=1ad8a962ac1da0a61b6f9fc3165d58218eeee9ce;hpb=f239aed5e674965691846e8ce3f187dd47523689;p=deb_dpdk.git diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h index 1ad8a962..8070d28d 100644 --- a/drivers/net/qede/base/mcp_public.h +++ b/drivers/net/qede/base/mcp_public.h @@ -28,19 +28,19 @@ typedef u32 offsize_t; /* In DWORDS !!! */ /* Offset from the beginning of the MCP scratchpad */ -#define OFFSIZE_OFFSET_SHIFT 0 +#define OFFSIZE_OFFSET_OFFSET 0 #define OFFSIZE_OFFSET_MASK 0x0000ffff /* Size of specific element (not the whole array if any) */ -#define OFFSIZE_SIZE_SHIFT 16 +#define OFFSIZE_SIZE_OFFSET 16 #define OFFSIZE_SIZE_MASK 0xffff0000 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ #define SECTION_OFFSET(_offsize) \ - ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2)) + ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2)) /* SECTION_SIZE is calculating the size in bytes out of offsize */ #define SECTION_SIZE(_offsize) \ - (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2) + (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2) /* SECTION_ADDR returns the GRC addr of a section, given offsize and index * within section @@ -59,7 +59,7 @@ struct eth_phy_cfg { /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ u32 speed; #define ETH_SPEED_AUTONEG 0 -#define ETH_SPEED_SMARTLINQ 0x8 +#define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */ u32 pause; /* bitmask */ #define ETH_PAUSE_NONE 0x0 @@ -84,38 +84,28 @@ struct eth_phy_cfg { /* Remote Serdes Loopback (RX to TX) */ #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) - /* Used to configure the EEE Tx LPI timer, has several modes of - * operation, according to bits 29:28 - * 2'b00: Timer will be configured by nvram, output will be the value - * from nvram. - * 2'b01: Timer will be configured by nvram, output will be in - * 16xmicroseconds. - * 2'b10: bits 1:0 contain an nvram value which will be used instead - * of the one located in the nvram. Output will be that value. - * 2'b11: bits 19:0 contain the idle timer in microseconds; output - * will be in 16xmicroseconds. - * Bits 31:30 should be 2'b11 in order for EEE to be enabled. - */ - u32 eee_mode; -#define EEE_MODE_TIMER_USEC_MASK (0x000fffff) -#define EEE_MODE_TIMER_USEC_OFFSET (0) -#define EEE_MODE_TIMER_USEC_BALANCED_TIME (0xa00) -#define EEE_MODE_TIMER_USEC_AGGRESSIVE_TIME (0x100) -#define EEE_MODE_TIMER_USEC_LATENCY_TIME (0x6000) -/* Set by the driver to request status timer will be in microseconds and and not - * in EEE policy definition + u32 eee_cfg; +/* EEE is enabled (configuration). Refer to eee_status->active for negotiated + * status */ -#define EEE_MODE_OUTPUT_TIME (1 << 28) -/* Set by the driver to override default nvm timer */ -#define EEE_MODE_OVERRIDE_NVRAM (1 << 29) -#define EEE_MODE_ENABLE_LPI (1 << 30) /* Set when */ -#define EEE_MODE_ADV_LPI (1 << 31) /* Set when EEE is enabled */ +#define EEE_CFG_EEE_ENABLED (1 << 0) +#define EEE_CFG_TX_LPI (1 << 1) +#define EEE_CFG_ADV_SPEED_1G (1 << 2) +#define EEE_CFG_ADV_SPEED_10G (1 << 3) +#define EEE_TX_TIMER_USEC_MASK (0xfffffff0) +#define EEE_TX_TIMER_USEC_OFFSET 4 +#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) +#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) +#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) + + u32 link_modes; /* Additional link modes */ +#define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */ }; struct port_mf_cfg { u32 dynamic_cfg; /* device control channel */ #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff -#define PORT_MF_CFG_OV_TAG_SHIFT 0 +#define PORT_MF_CFG_OV_TAG_OFFSET 0 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK u32 reserved[1]; @@ -274,11 +264,11 @@ struct couple_mode_teaming { /************************************** * LLDP and DCBX HSI structures **************************************/ -#define LLDP_CHASSIS_ID_STAT_LEN 4 -#define LLDP_PORT_ID_STAT_LEN 4 +#define LLDP_CHASSIS_ID_STAT_LEN 4 +#define LLDP_PORT_ID_STAT_LEN 4 #define DCBX_MAX_APP_PROTOCOL 32 -#define MAX_SYSTEM_LLDP_TLV_DATA 32 - +#define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/ +#define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ typedef enum _lldp_agent_e { LLDP_NEAREST_BRIDGE = 0, LLDP_NEAREST_NON_TPMR_BRIDGE, @@ -289,15 +279,15 @@ typedef enum _lldp_agent_e { struct lldp_config_params_s { u32 config; #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff -#define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 +#define LLDP_CONFIG_TX_INTERVAL_OFFSET 0 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 -#define LLDP_CONFIG_HOLD_SHIFT 8 +#define LLDP_CONFIG_HOLD_OFFSET 8 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 -#define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 +#define LLDP_CONFIG_MAX_CREDIT_OFFSET 12 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 -#define LLDP_CONFIG_ENABLE_RX_SHIFT 30 +#define LLDP_CONFIG_ENABLE_RX_OFFSET 30 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 -#define LLDP_CONFIG_ENABLE_TX_SHIFT 31 +#define LLDP_CONFIG_ENABLE_TX_OFFSET 31 /* Holds local Chassis ID TLV header, subtype and 9B of payload. * If firtst byte is 0, then we will use default chassis ID */ @@ -321,17 +311,17 @@ struct lldp_status_params_s { struct dcbx_ets_feature { u32 flags; #define DCBX_ETS_ENABLED_MASK 0x00000001 -#define DCBX_ETS_ENABLED_SHIFT 0 +#define DCBX_ETS_ENABLED_OFFSET 0 #define DCBX_ETS_WILLING_MASK 0x00000002 -#define DCBX_ETS_WILLING_SHIFT 1 +#define DCBX_ETS_WILLING_OFFSET 1 #define DCBX_ETS_ERROR_MASK 0x00000004 -#define DCBX_ETS_ERROR_SHIFT 2 +#define DCBX_ETS_ERROR_OFFSET 2 #define DCBX_ETS_CBS_MASK 0x00000008 -#define DCBX_ETS_CBS_SHIFT 3 +#define DCBX_ETS_CBS_OFFSET 3 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 -#define DCBX_ETS_MAX_TCS_SHIFT 4 +#define DCBX_ETS_MAX_TCS_OFFSET 4 #define DCBX_OOO_TC_MASK 0x00000f00 -#define DCBX_OOO_TC_SHIFT 8 +#define DCBX_OOO_TC_OFFSET 8 /* Entries in tc table are orginized that the left most is pri 0, right most is * prio 7 */ @@ -363,7 +353,7 @@ struct dcbx_ets_feature { struct dcbx_app_priority_entry { u32 entry; #define DCBX_APP_PRI_MAP_MASK 0x000000ff -#define DCBX_APP_PRI_MAP_SHIFT 0 +#define DCBX_APP_PRI_MAP_OFFSET 0 #define DCBX_APP_PRI_0 0x01 #define DCBX_APP_PRI_1 0x02 #define DCBX_APP_PRI_2 0x04 @@ -373,11 +363,11 @@ struct dcbx_app_priority_entry { #define DCBX_APP_PRI_6 0x40 #define DCBX_APP_PRI_7 0x80 #define DCBX_APP_SF_MASK 0x00000300 -#define DCBX_APP_SF_SHIFT 8 +#define DCBX_APP_SF_OFFSET 8 #define DCBX_APP_SF_ETHTYPE 0 #define DCBX_APP_SF_PORT 1 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 -#define DCBX_APP_SF_IEEE_SHIFT 12 +#define DCBX_APP_SF_IEEE_OFFSET 12 #define DCBX_APP_SF_IEEE_RESERVED 0 #define DCBX_APP_SF_IEEE_ETHTYPE 1 #define DCBX_APP_SF_IEEE_TCP_PORT 2 @@ -385,7 +375,7 @@ struct dcbx_app_priority_entry { #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 -#define DCBX_APP_PROTOCOL_ID_SHIFT 16 +#define DCBX_APP_PROTOCOL_ID_OFFSET 16 }; @@ -393,19 +383,19 @@ struct dcbx_app_priority_entry { struct dcbx_app_priority_feature { u32 flags; #define DCBX_APP_ENABLED_MASK 0x00000001 -#define DCBX_APP_ENABLED_SHIFT 0 +#define DCBX_APP_ENABLED_OFFSET 0 #define DCBX_APP_WILLING_MASK 0x00000002 -#define DCBX_APP_WILLING_SHIFT 1 +#define DCBX_APP_WILLING_OFFSET 1 #define DCBX_APP_ERROR_MASK 0x00000004 -#define DCBX_APP_ERROR_SHIFT 2 +#define DCBX_APP_ERROR_OFFSET 2 /* Not in use #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 - #define DCBX_APP_DEFAULT_PRI_SHIFT 8 + #define DCBX_APP_DEFAULT_PRI_OFFSET 8 */ #define DCBX_APP_MAX_TCS_MASK 0x0000f000 -#define DCBX_APP_MAX_TCS_SHIFT 12 +#define DCBX_APP_MAX_TCS_OFFSET 12 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 -#define DCBX_APP_NUM_ENTRIES_SHIFT 16 +#define DCBX_APP_NUM_ENTRIES_OFFSET 16 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; }; @@ -416,7 +406,7 @@ struct dcbx_features { /* PFC feature */ u32 pfc; #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff -#define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 +#define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 @@ -427,17 +417,17 @@ struct dcbx_features { #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 -#define DCBX_PFC_FLAGS_SHIFT 8 +#define DCBX_PFC_FLAGS_OFFSET 8 #define DCBX_PFC_CAPS_MASK 0x00000f00 -#define DCBX_PFC_CAPS_SHIFT 8 +#define DCBX_PFC_CAPS_OFFSET 8 #define DCBX_PFC_MBC_MASK 0x00004000 -#define DCBX_PFC_MBC_SHIFT 14 +#define DCBX_PFC_MBC_OFFSET 14 #define DCBX_PFC_WILLING_MASK 0x00008000 -#define DCBX_PFC_WILLING_SHIFT 15 +#define DCBX_PFC_WILLING_OFFSET 15 #define DCBX_PFC_ENABLED_MASK 0x00010000 -#define DCBX_PFC_ENABLED_SHIFT 16 +#define DCBX_PFC_ENABLED_OFFSET 16 #define DCBX_PFC_ERROR_MASK 0x00020000 -#define DCBX_PFC_ERROR_SHIFT 17 +#define DCBX_PFC_ERROR_OFFSET 17 /* APP feature */ struct dcbx_app_priority_feature app; @@ -446,10 +436,12 @@ struct dcbx_features { struct dcbx_local_params { u32 config; #define DCBX_CONFIG_VERSION_MASK 0x00000007 -#define DCBX_CONFIG_VERSION_SHIFT 0 +#define DCBX_CONFIG_VERSION_OFFSET 0 #define DCBX_CONFIG_VERSION_DISABLED 0 #define DCBX_CONFIG_VERSION_IEEE 1 #define DCBX_CONFIG_VERSION_CEE 2 +#define DCBX_CONFIG_VERSION_DYNAMIC \ + (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE) #define DCBX_CONFIG_VERSION_STATIC 4 u32 flags; @@ -461,7 +453,7 @@ struct dcbx_mib { u32 flags; /* #define DCBX_CONFIG_VERSION_MASK 0x00000007 - #define DCBX_CONFIG_VERSION_SHIFT 0 + #define DCBX_CONFIG_VERSION_OFFSET 0 #define DCBX_CONFIG_VERSION_DISABLED 0 #define DCBX_CONFIG_VERSION_IEEE 1 #define DCBX_CONFIG_VERSION_CEE 2 @@ -472,19 +464,49 @@ struct dcbx_mib { }; struct lldp_system_tlvs_buffer_s { - u16 valid; - u16 length; + u32 flags; +#define LLDP_SYSTEM_TLV_VALID_MASK 0x1 +#define LLDP_SYSTEM_TLV_VALID_OFFSET 0 +/* This bit defines if system TLVs are instead of mandatory TLVS or in + * addition to them. Set 1 for replacing mandatory TLVs + */ +#define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 +#define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1 +#define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 +#define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; }; +/* Since this struct is written by MFW and read by driver need to add + * sequence guards (as in case of DCBX MIB) + */ +struct lldp_received_tlvs_s { + u32 prefix_seq_num; + u32 length; + u32 tlvs_buffer[MAX_TLV_BUFFER]; + u32 suffix_seq_num; +}; + struct dcb_dscp_map { u32 flags; #define DCB_DSCP_ENABLE_MASK 0x1 -#define DCB_DSCP_ENABLE_SHIFT 0 +#define DCB_DSCP_ENABLE_OFFSET 0 #define DCB_DSCP_ENABLE 1 u32 dscp_pri_map[8]; }; +/************************************** + * Attributes commands + **************************************/ + +enum _attribute_commands_e { + ATTRIBUTE_CMD_READ = 0, + ATTRIBUTE_CMD_WRITE, + ATTRIBUTE_CMD_READ_CLEAR, + ATTRIBUTE_CMD_CLEAR, + ATTRIBUTE_NUM_OF_COMMANDS +}; + /**************************************/ /* */ /* P U B L I C G L O B A L */ @@ -512,12 +534,12 @@ struct public_global { #define MDUMP_REASON_DUMP_AGED (1 << 2) u32 ext_phy_upgrade_fw; #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) -#define EXT_PHY_FW_UPGRADE_STATUS_SHIFT (0) +#define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0) #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) -#define EXT_PHY_FW_UPGRADE_TYPE_SHIFT (16) +#define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16) }; /**************************************/ @@ -567,9 +589,9 @@ struct public_path { /* Reset on mcp reset, and incremented for eveny process kill event. */ u32 process_kill; #define PROCESS_KILL_COUNTER_MASK 0x0000ffff -#define PROCESS_KILL_COUNTER_SHIFT 0 +#define PROCESS_KILL_COUNTER_OFFSET 0 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 -#define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 +#define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) }; @@ -697,6 +719,8 @@ struct public_port { #define LFA_SPEED_MISMATCH (1 << 3) #define LFA_FLOW_CTRL_MISMATCH (1 << 4) #define LFA_ADV_SPEED_MISMATCH (1 << 5) +#define LFA_EEE_MISMATCH (1 << 6) +#define LFA_LINK_MODES_MISMATCH (1 << 7) #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 #define LINK_FLAP_COUNT_OFFSET 16 @@ -721,13 +745,13 @@ struct public_port { u32 fc_npiv_nvram_tbl_size; u32 transceiver_data; #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF -#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 +#define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 -#define ETH_TRANSCEIVER_TYPE_SHIFT 0x00000008 +#define ETH_TRANSCEIVER_TYPE_OFFSET 0x00000008 #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF /* 1G Passive copper cable */ @@ -775,6 +799,7 @@ struct public_port { #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 +#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 @@ -787,38 +812,55 @@ struct public_port { u32 wol_pkt_details; struct dcb_dscp_map dcb_dscp_map; - /* the status of EEE auto-negotiation - * bits 19:0 the configured tx-lpi entry timer value. Depends on bit 31. - * bits 23:20 the speeds advertised for EEE. - * bits 27:24 the speeds the Link partner advertised for EEE. - * The supported/adv. modes in bits 27:19 originate from the - * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). - * bit 28 when 1'b1 EEE was requested. - * bit 29 when 1'b1 tx lpi was requested. - * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted if 30:29 - * are 2'b11. - * bit 31 - When 1'b0 bits 15:0 contain - * NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_XXX define as value. - * When 1'b1 those bits contains a value times 16 microseconds. - */ u32 eee_status; -#define EEE_TIMER_MASK 0x000fffff -#define EEE_ADV_STATUS_MASK 0x00f00000 -#define EEE_1G_ADV (1 << 1) -#define EEE_10G_ADV (1 << 2) -#define EEE_ADV_STATUS_SHIFT 20 -#define EEE_LP_ADV_STATUS_MASK 0x0f000000 -#define EEE_LP_ADV_STATUS_SHIFT 24 -#define EEE_REQUESTED_BIT 0x10000000 -#define EEE_LPI_REQUESTED_BIT 0x20000000 -#define EEE_ACTIVE_BIT 0x40000000 -#define EEE_TIME_OUTPUT_BIT 0x80000000 +/* Set when EEE negotiation is complete. */ +#define EEE_ACTIVE_BIT (1 << 0) + +/* Shows the Local Device EEE capabilities */ +#define EEE_LD_ADV_STATUS_MASK 0x000000f0 +#define EEE_LD_ADV_STATUS_OFFSET 4 + #define EEE_1G_ADV (1 << 1) + #define EEE_10G_ADV (1 << 2) +/* Same values as in EEE_LD_ADV, but for Link Parter */ +#define EEE_LP_ADV_STATUS_MASK 0x00000f00 +#define EEE_LP_ADV_STATUS_OFFSET 8 + +/* Supported speeds for EEE */ +#define EEE_SUPPORTED_SPEED_MASK 0x0000f000 +#define EEE_SUPPORTED_SPEED_OFFSET 12 + #define EEE_1G_SUPPORTED (1 << 1) + #define EEE_10G_SUPPORTED (1 << 2) u32 eee_remote; /* Used for EEE in LLDP */ #define EEE_REMOTE_TW_TX_MASK 0x0000ffff -#define EEE_REMOTE_TW_TX_SHIFT 0 +#define EEE_REMOTE_TW_TX_OFFSET 0 #define EEE_REMOTE_TW_RX_MASK 0xffff0000 -#define EEE_REMOTE_TW_RX_SHIFT 16 +#define EEE_REMOTE_TW_RX_OFFSET 16 + + u32 module_info; +#define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF +#define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0 +#define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2) +#define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3) +#define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4) +#define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5) +#define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) +#define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 +#define ETH_TRANSCEIVER_IDENT_OFFSET 8 + + u32 oem_cfg_port; +#define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 +#define OEM_CFG_CHANNEL_TYPE_OFFSET 0 +#define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 +#define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 + +#define OEM_CFG_SCHED_TYPE_MASK 0x0000000C +#define OEM_CFG_SCHED_TYPE_OFFSET 2 +#define OEM_CFG_SCHED_TYPE_ETS 0x1 +#define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 + + struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; + u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; }; /**************************************/ @@ -857,11 +899,11 @@ struct public_func { /* function 0 of each port cannot be hidden */ #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 -#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 +#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 -#define FUNC_MF_CFG_PROTOCOL_SHIFT 4 +#define FUNC_MF_CFG_PROTOCOL_OFFSET 4 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 @@ -871,18 +913,20 @@ struct public_func { /* MINBW, MAXBW */ /* value range - 0..100, increments in 1 % */ #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 -#define FUNC_MF_CFG_MIN_BW_SHIFT 8 +#define FUNC_MF_CFG_MIN_BW_OFFSET 8 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 -#define FUNC_MF_CFG_MAX_BW_SHIFT 16 +#define FUNC_MF_CFG_MAX_BW_OFFSET 16 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 u32 status; -#define FUNC_STATUS_VLINK_DOWN 0x00000001 +#define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 +#define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002 +#define FUNC_STATUS_FORCED_LINK 0x00000004 u32 mac_upper; /* MAC */ #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff -#define FUNC_MF_CFG_UPPERMAC_SHIFT 0 +#define FUNC_MF_CFG_UPPERMAC_OFFSET 0 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK u32 mac_lower; #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff @@ -895,7 +939,7 @@ struct public_func { u32 ovlan_stag; /* tags */ #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff -#define FUNC_MF_CFG_OV_STAG_SHIFT 0 +#define FUNC_MF_CFG_OV_STAG_OFFSET 0 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK u32 pf_allocation; /* vf per pf */ @@ -912,29 +956,46 @@ struct public_func { u32 drv_id; #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff -#define DRV_ID_PDA_COMP_VER_SHIFT 0 +#define DRV_ID_PDA_COMP_VER_OFFSET 0 #define LOAD_REQ_HSI_VERSION 2 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 -#define DRV_ID_MCP_HSI_VER_SHIFT 16 +#define DRV_ID_MCP_HSI_VER_OFFSET 16 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ - DRV_ID_MCP_HSI_VER_SHIFT) + DRV_ID_MCP_HSI_VER_OFFSET) #define DRV_ID_DRV_TYPE_MASK 0x7f000000 -#define DRV_ID_DRV_TYPE_SHIFT 24 -#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT) -#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT) +#define DRV_ID_DRV_TYPE_OFFSET 24 +#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET) +#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET) #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 -#define DRV_ID_DRV_INIT_HW_SHIFT 31 -#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) +#define DRV_ID_DRV_INIT_HW_OFFSET 31 +#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET) + + u32 oem_cfg_func; +#define OEM_CFG_FUNC_TC_MASK 0x0000000F +#define OEM_CFG_FUNC_TC_OFFSET 0 +#define OEM_CFG_FUNC_TC_0 0x0 +#define OEM_CFG_FUNC_TC_1 0x1 +#define OEM_CFG_FUNC_TC_2 0x2 +#define OEM_CFG_FUNC_TC_3 0x3 +#define OEM_CFG_FUNC_TC_4 0x4 +#define OEM_CFG_FUNC_TC_5 0x5 +#define OEM_CFG_FUNC_TC_6 0x6 +#define OEM_CFG_FUNC_TC_7 0x7 + +#define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 +#define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 +#define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 +#define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 }; /**************************************/ @@ -1019,13 +1080,13 @@ struct ocbb_data_stc { #define MFW_SENSOR_LOCATION_EXTERNAL 2 #define MFW_SENSOR_LOCATION_SFP 3 -#define SENSOR_LOCATION_SHIFT 0 +#define SENSOR_LOCATION_OFFSET 0 #define SENSOR_LOCATION_MASK 0x000000ff -#define THRESHOLD_HIGH_SHIFT 8 +#define THRESHOLD_HIGH_OFFSET 8 #define THRESHOLD_HIGH_MASK 0x0000ff00 -#define CRITICAL_TEMPERATURE_SHIFT 16 +#define CRITICAL_TEMPERATURE_OFFSET 16 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 -#define CURRENT_TEMP_SHIFT 24 +#define CURRENT_TEMP_OFFSET 24 #define CURRENT_TEMP_MASK 0xff000000 struct temperature_status_stc { u32 num_of_sensors; @@ -1090,18 +1151,18 @@ struct load_req_stc { u32 fw_ver; u32 misc0; #define LOAD_REQ_ROLE_MASK 0x000000FF -#define LOAD_REQ_ROLE_SHIFT 0 +#define LOAD_REQ_ROLE_OFFSET 0 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 -#define LOAD_REQ_LOCK_TO_SHIFT 8 +#define LOAD_REQ_LOCK_TO_OFFSET 8 #define LOAD_REQ_LOCK_TO_DEFAULT 0 #define LOAD_REQ_LOCK_TO_NONE 255 #define LOAD_REQ_FORCE_MASK 0x000F0000 -#define LOAD_REQ_FORCE_SHIFT 16 +#define LOAD_REQ_FORCE_OFFSET 16 #define LOAD_REQ_FORCE_NONE 0 #define LOAD_REQ_FORCE_PF 1 #define LOAD_REQ_FORCE_ALL 2 #define LOAD_REQ_FLAGS0_MASK 0x00F00000 -#define LOAD_REQ_FLAGS0_SHIFT 20 +#define LOAD_REQ_FLAGS0_OFFSET 20 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) }; @@ -1111,14 +1172,27 @@ struct load_rsp_stc { u32 fw_ver; u32 misc0; #define LOAD_RSP_ROLE_MASK 0x000000FF -#define LOAD_RSP_ROLE_SHIFT 0 +#define LOAD_RSP_ROLE_OFFSET 0 #define LOAD_RSP_HSI_MASK 0x0000FF00 -#define LOAD_RSP_HSI_SHIFT 8 +#define LOAD_RSP_HSI_OFFSET 8 #define LOAD_RSP_FLAGS0_MASK 0x000F0000 -#define LOAD_RSP_FLAGS0_SHIFT 16 +#define LOAD_RSP_FLAGS0_OFFSET 16 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) }; +struct mdump_retain_data_stc { + u32 valid; + u32 epoch; + u32 pf; + u32 status; +}; + +struct attribute_cmd_write_stc { + u32 val; + u32 mask; + u32 offset; +}; + union drv_union_data { struct mcp_mac wol_mac; /* UNLOAD_DONE */ @@ -1149,6 +1223,8 @@ union drv_union_data { struct load_req_stc load_req; struct load_rsp_stc load_rsp; + struct mdump_retain_data_stc mdump_retain; + struct attribute_cmd_write_stc attribute_cmd_write; /* ... */ }; @@ -1166,8 +1242,8 @@ struct public_drv_mb { /* - DONT_CARE - Don't flap the link if up */ #define DRV_MSG_CODE_LINK_RESET 0x23000000 - /* Vitaly: LLDP commands */ #define DRV_MSG_CODE_SET_LLDP 0x24000000 +#define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000 #define DRV_MSG_CODE_SET_DCBX 0x25000000 /* OneView feature driver HSI*/ #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 @@ -1183,24 +1259,26 @@ struct public_drv_mb { */ #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 +#define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 /*deprecated don't use*/ #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 +#define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 /* Param should be set to the transaction size (up to 64 bytes) */ #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 /* MFW will place the file offset and len in file_att struct */ #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 -/* Read 32bytes of nvram data. Param is [0:23] – Offset [24:31] – - * Len in Bytes +/* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] - + * ??? Len in Bytes */ #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 -/* Writes up to 32Bytes to nvram. Param is [0:23] – Offset [24:31] – - * Len in Bytes. In case this address is in the range of secured file in +/* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] + * ??? Len in Bytes. In case this address is in the range of secured file in * secured mode, the operation will fail */ #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 @@ -1242,7 +1320,7 @@ struct public_drv_mb { * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */ #define DRV_MSG_CODE_GET_VMAC 0x00120000 -#define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4 +#define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 @@ -1270,9 +1348,9 @@ struct public_drv_mb { /* Set function BW, params[15:8] - min, params[7:0] - max */ #define DRV_MSG_CODE_SET_BW 0x00190000 #define BW_MAX_MASK 0x000000ff -#define BW_MAX_SHIFT 0 +#define BW_MAX_OFFSET 0 #define BW_MIN_MASK 0x0000ff00 -#define BW_MIN_SHIFT 8 +#define BW_MIN_OFFSET 8 /* When param is set to 1, all parities will be masked(disabled). When params * are set to 0, parities will be unmasked again. @@ -1305,9 +1383,9 @@ struct public_drv_mb { #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F -#define RESOURCE_CMD_REQ_RESC_SHIFT 0 +#define RESOURCE_CMD_REQ_RESC_OFFSET 0 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 -#define RESOURCE_CMD_REQ_OPCODE_SHIFT 5 +#define RESOURCE_CMD_REQ_OPCODE_OFFSET 5 /* request resource ownership with default aging */ #define RESOURCE_OPCODE_REQ 1 /* request resource ownership without aging */ @@ -1318,12 +1396,12 @@ struct public_drv_mb { /* force resource release */ #define RESOURCE_OPCODE_FORCE_RELEASE 5 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 -#define RESOURCE_CMD_REQ_AGE_SHIFT 8 +#define RESOURCE_CMD_REQ_AGE_OFFSET 8 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF -#define RESOURCE_CMD_RSP_OWNER_SHIFT 0 +#define RESOURCE_CMD_RSP_OWNER_OFFSET 0 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 -#define RESOURCE_CMD_RSP_OPCODE_SHIFT 8 +#define RESOURCE_CMD_RSP_OPCODE_OFFSET 8 /* resource is free and granted to requester */ #define RESOURCE_OPCODE_GNT 1 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, @@ -1361,6 +1439,8 @@ struct public_drv_mb { #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 /* Clear all logs */ #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 +#define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */ +#define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */ #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ /* Param: [0:15] - gpio number */ #define DRV_MSG_CODE_GPIO_INFO 0x00270000 @@ -1368,14 +1448,28 @@ struct public_drv_mb { #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 /* Value should be placed in union */ #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 -#define DRV_MB_PARAM_ADDR_SHIFT 0 +#define DRV_MB_PARAM_ADDR_OFFSET 0 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF -#define DRV_MB_PARAM_DEVAD_SHIFT 16 +#define DRV_MB_PARAM_DEVAD_OFFSET 16 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 -#define DRV_MB_PARAM_PORT_SHIFT 21 +#define DRV_MB_PARAM_PORT_OFFSET 21 #define DRV_MB_PARAM_PORT_MASK 0x00600000 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 +#define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ +/* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ +#define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 +/* return FW_MB_PARAM_FEATURE_SUPPORT_* */ +#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 +#define DRV_MSG_CODE_READ_WOL_REG 0X00320000 +#define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 +#define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 +/* Param: [0:23] Attribute key, [24:31] Attribute sub command */ +#define DRV_MSG_CODE_ATTRIBUTE 0x00350000 + +/* Param: Password len. Union: Plain Password */ +#define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 + #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff u32 drv_mb_param; @@ -1393,45 +1487,56 @@ struct public_drv_mb { #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 /* LLDP / DCBX params*/ + /* To be used with SET_LLDP command */ #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 -#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 +#define DRV_MB_PARAM_LLDP_SEND_OFFSET 0 + /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */ #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 -#define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1 +#define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1 + /* To be used with REGISTER_LLDP_TLVS_RX command */ +#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 +#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0 +#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 +#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4 + /* To be used with SET_DCBX command */ #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 -#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 +#define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF -#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0 +#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 -#define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0 +#define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF -#define DRV_MB_PARAM_NVM_LEN_SHIFT 24 +#define DRV_MB_PARAM_NVM_LEN_OFFSET 24 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 -#define DRV_MB_PARAM_PHY_ADDR_SHIFT 0 +#define DRV_MB_PARAM_PHY_ADDR_OFFSET 0 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF -#define DRV_MB_PARAM_PHY_LANE_SHIFT 16 +#define DRV_MB_PARAM_PHY_LANE_OFFSET 16 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 -#define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29 +#define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 -#define DRV_MB_PARAM_PHY_PORT_SHIFT 30 +#define DRV_MB_PARAM_PHY_PORT_OFFSET 30 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 -#define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0 +#define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF -#define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8 +#define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 - /* configure vf MSIX params*/ -#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 + /* configure vf MSIX params BB */ +#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF -#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 +#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 + /* configure vf MSIX for PF params AH*/ +#define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0 +#define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF /* OneView configuration parametres */ -#define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 +#define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 @@ -1442,7 +1547,7 @@ struct public_drv_mb { #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 -#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0 +#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) @@ -1455,17 +1560,17 @@ struct public_drv_mb { #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 -#define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0 +#define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF -#define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 +#define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF -#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 +#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 /* Not Installed*/ @@ -1476,36 +1581,36 @@ struct public_drv_mb { /* installed and active */ #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 -#define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 +#define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 -#define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0 +#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 -#define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2 +#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC -#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8 +#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 -#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16 +#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 -#define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0 +#define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF -#define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16 +#define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 -#define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16 +#define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 -#define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24 +#define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 /* Resource Allocation params - Driver version support*/ #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 -#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 +#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF -#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 +#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 @@ -1518,11 +1623,27 @@ struct public_drv_mb { #define DRV_MB_PARAM_BIST_RC_FAILED 2 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 -#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 +#define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF -#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 +#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 +#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF +#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 +/* driver supports SmartLinQ parameter */ +#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 +/* driver supports EEE parameter */ +#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 +#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 +#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16 +/* driver supports virtual link parameter */ +#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 + /* Driver attributes params */ +#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 +#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF +#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 +#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 + u32 fw_mb_header; #define FW_MSG_CODE_MASK 0xffff0000 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 @@ -1545,6 +1666,7 @@ struct public_drv_mb { #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 +#define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 @@ -1597,6 +1719,7 @@ struct public_drv_mb { #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 #define FW_MSG_CODE_OK 0x00160000 +#define FW_MSG_CODE_ERROR 0x00170000 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 @@ -1628,16 +1751,39 @@ struct public_drv_mb { #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 + +#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 +#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 + +#define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 +#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 +#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 +#define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 +#define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 + #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff +#define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 +#define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 u32 fw_mb_param; /* Resource Allocation params - MFW version support */ #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 -#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 +#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF -#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 +#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 + +/* get MFW feature support response */ +/* MFW supports SmartLinQ */ +#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 +/* MFW supports EEE */ +#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 +/* MFW support complete IGU cleanup upon FLR */ +#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP 0x00000080 +/* MFW supports virtual link */ +#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 +#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) u32 drv_pulse_mb; #define DRV_PULSE_SEQ_MASK 0x00007fff @@ -1702,6 +1848,9 @@ enum MFW_DRV_MSG_TYPE { MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, + MFW_DRV_MSG_GET_TLV_REQ, + MFW_DRV_MSG_OEM_CFG_UPDATE, + MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, MFW_DRV_MSG_MAX };