X-Git-Url: https://gerrit.fd.io/r/gitweb?a=blobdiff_plain;f=test%2Ftest_lb.py;h=e653b60b0ab62c4cb0e578f68c53499143e359b7;hb=97b1a27130d540ef7046638b9b3e01d83be71c14;hp=3e7f5e13faf78fd083e396b6f1c322bdb16180e7;hpb=7bb873a4cc068a6cc3c9d0e1d32987c5f8003904;p=vpp.git

diff --git a/test/test_lb.py b/test/test_lb.py
index 3e7f5e13faf..e653b60b0ab 100644
--- a/test/test_lb.py
+++ b/test/test_lb.py
@@ -69,10 +69,10 @@ class TestLB(VppTestCase):
                 UDP(sport=10000 + id, dport=20000 + id))
 
     def generatePackets(self, src_if, isv4):
-        self.packet_infos = {}
+        self.reset_packet_infos()
         pkts = []
         for pktid in self.packets:
-            info = self.create_packet_info(src_if.sw_if_index, pktid)
+            info = self.create_packet_info(src_if, self.pg1)
             payload = self.info_to_payload(info)
             ip = self.getIPv4Flow(pktid) if isv4 else self.getIPv6Flow(pktid)
             packet = (Ether(dst=src_if.local_mac, src=src_if.remote_mac) /
@@ -90,17 +90,13 @@ class TestLB(VppTestCase):
         self.assertEqual(gre.version, 0)
         inner = IPver(str(gre.payload))
         payload_info = self.payload_to_info(str(inner[Raw]))
-        self.info = self.get_next_packet_info_for_interface2(
-            self.pg0.sw_if_index, payload_info.dst, self.info)
+        self.info = self.packet_infos[payload_info.index]
+        self.assertEqual(payload_info.src, self.pg0.sw_if_index)
         self.assertEqual(str(inner), str(self.info.data[IPver]))
 
     def checkCapture(self, gre4, isv4):
-        out = self.pg0.get_capture()
-        # This check is edited because RA appears in output, maybe disable RA?
-        # self.assertEqual(len(out), 0)
-        self.assertLess(len(out), 20)
-        out = self.pg1.get_capture()
-        self.assertEqual(len(out), len(self.packets))
+        self.pg0.assert_nothing_captured()
+        out = self.pg1.get_capture(len(self.packets))
 
         load = [0] * len(self.ass)
         self.info = None
@@ -146,7 +142,7 @@ class TestLB(VppTestCase):
         # is not completly biased.
         for asid in self.ass:
             if load[asid] < len(self.packets) / (len(self.ass) * 2):
-                self.log(
+                self.logger.error(
                     "ASS is not balanced: load[%d] = %d" % (asid, load[asid]))
                 raise Exception("Load Balancer algorithm is biased")
 
@@ -166,6 +162,7 @@ class TestLB(VppTestCase):
             for asid in self.ass:
                 self.vapi.cli("lb as 90.0.0.0/8 10.0.0.%u del" % (asid))
             self.vapi.cli("lb vip 90.0.0.0/8 encap gre4 del")
+            self.vapi.cli("test lb flowtable flush")
 
     def test_lb_ip6_gre4(self):
         """ Load Balancer IP6 GRE4 """
@@ -184,6 +181,7 @@ class TestLB(VppTestCase):
             for asid in self.ass:
                 self.vapi.cli("lb as 2001::/16 10.0.0.%u del" % (asid))
             self.vapi.cli("lb vip 2001::/16 encap gre4 del")
+            self.vapi.cli("test lb flowtable flush")
 
     def test_lb_ip4_gre6(self):
         """ Load Balancer IP4 GRE6 """
@@ -199,8 +197,9 @@ class TestLB(VppTestCase):
             self.checkCapture(gre4=False, isv4=True)
         finally:
             for asid in self.ass:
-                self.vapi.cli("lb as 90.0.0.0/8 2002::%u" % (asid))
+                self.vapi.cli("lb as 90.0.0.0/8 2002::%u del" % (asid))
             self.vapi.cli("lb vip 90.0.0.0/8 encap gre6 del")
+            self.vapi.cli("test lb flowtable flush")
 
     def test_lb_ip6_gre6(self):
         """ Load Balancer IP6 GRE6 """
@@ -218,3 +217,4 @@ class TestLB(VppTestCase):
             for asid in self.ass:
                 self.vapi.cli("lb as 2001::/16 2002::%u del" % (asid))
             self.vapi.cli("lb vip 2001::/16 encap gre6 del")
+            self.vapi.cli("test lb flowtable flush")