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(parent: 23a7412) | patch
l2: fix latency issue casued by unnecesary read of previous cacheline 52/3952/2
authorDamjan Marion <damarion@cisco.com>
Thu, 24 Nov 2016 21:20:05 +0000 (22:20 +0100)
committerNeale Ranns <nranns@cisco.com>
Fri, 25 Nov 2016 09:27:31 +0000 (09:27 +0000)
commit30230dd7f854e77008b257c8be1de648e473338e
tree53e99fc7b066593ae9672cfbb80511362c53b450tree | snapshot
parent23a7412bda2c14b21deda66bc5555c9ee680dec8commit | diff
l2: fix latency issue casued by unnecesary read of previous cacheline

In majority of cases ethernet header sits at the beggining of cacheline.
Reading (dst_mac - 2) into 64 bit register is much more expensive
than doing simple bitwise shift, specially if previous cacheline is
not prefetched.

Change-Id: I35e53eae735098fb917a87c307e60a87e76e460f
Signed-off-by: Damjan Marion <damarion@cisco.com>
vnet/vnet/l2/l2_fib.h diff | blob | history
Vector Packet Processing