Fixes issues on systems with 128-byte cacheline.
Type: fix
Change-Id: I33689ffa5ef0a879b4bf93c25d48618dd43daf58
Signed-off-by: Damjan Marion <damarion@cisco.com>
/** part of buffer metadata which is initialized on alloc ends here. */
STRUCT_MARK (template_end);
/** part of buffer metadata which is initialized on alloc ends here. */
STRUCT_MARK (template_end);
- /** start of 2nd cache line */
- CLIB_CACHE_LINE_ALIGN_MARK (cacheline1);
+ /** start of 2nd half (2nd cacheline on systems where cacheline size is 64) */
+ CLIB_ALIGN_MARK (second_half, 64);
/** Specifies trace buffer handle if VLIB_PACKET_IS_TRACED flag is
* set. */
/** Specifies trace buffer handle if VLIB_PACKET_IS_TRACED flag is
* set. */
/**< More opaque data, see ../vnet/vnet/buffer.h */
u32 opaque2[14];
/**< More opaque data, see ../vnet/vnet/buffer.h */
u32 opaque2[14];
- /** start of third cache line */
- CLIB_CACHE_LINE_ALIGN_MARK (cacheline2);
+ /** start of buffer headroom */
+ CLIB_ALIGN_MARK (headroom, 64);
/** Space for inserting data before buffer start. Packet rewrite string
* will be rewritten backwards and may extend back before
/** Space for inserting data before buffer start. Packet rewrite string
* will be rewritten backwards and may extend back before
+STATIC_ASSERT_SIZEOF (vlib_buffer_t, 128 + VLIB_BUFFER_PRE_DATA_SIZE);
+STATIC_ASSERT (VLIB_BUFFER_PRE_DATA_SIZE % CLIB_CACHE_LINE_BYTES == 0,
+ "VLIB_BUFFER_PRE_DATA_SIZE must be divisible by cache line size");
+
#define VLIB_BUFFER_HDR_SIZE (sizeof(vlib_buffer_t) - VLIB_BUFFER_PRE_DATA_SIZE)
/** \brief Prefetch buffer metadata.
#define VLIB_BUFFER_HDR_SIZE (sizeof(vlib_buffer_t) - VLIB_BUFFER_PRE_DATA_SIZE)
/** \brief Prefetch buffer metadata.