-test_perf_event_bundle_t perf_bundles[] = { {
- .config[0] = PERF_COUNT_HW_CPU_CYCLES,
- .config[1] = PERF_COUNT_HW_INSTRUCTIONS,
- .config[2] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
- .config[3] = PERF_COUNT_HW_BRANCH_MISSES,
- .n_events = 4,
- .format_fn = format_test_perf_bundle_default,
-} };
+static u8 *
+format_test_perf_bundle_core_power (u8 *s, va_list *args)
+{
+ test_perf_event_bundle_t __clib_unused *b =
+ va_arg (*args, test_perf_event_bundle_t *);
+ test_perf_t __clib_unused *tp = va_arg (*args, test_perf_t *);
+ u64 *data = va_arg (*args, u64 *);
+
+ if (data)
+ s = format (s, "%7.1f %%", (f64) 100 * data[1] / data[0]);
+ else
+ s = format (s, "%9s", "Level 0");
+
+ if (data)
+ s = format (s, "%8.1f %%", (f64) 100 * data[2] / data[0]);
+ else
+ s = format (s, "%9s", "Level 1");
+
+ if (data)
+ s = format (s, "%7.1f %%", (f64) 100 * data[3] / data[0]);
+ else
+ s = format (s, "%9s", "Level 2");
+
+ return s;
+}
+
+test_perf_event_bundle_t perf_bundles[] = {
+ {
+ .name = "default",
+ .desc = "IPC, Clocks/Operatiom, Instr/Operation, Branch Total & Miss",
+ .type = PERF_TYPE_HARDWARE,
+ .config[0] = PERF_COUNT_HW_CPU_CYCLES,
+ .config[1] = PERF_COUNT_HW_INSTRUCTIONS,
+ .config[2] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
+ .config[3] = PERF_COUNT_HW_BRANCH_MISSES,
+ .n_events = 4,
+ .format_fn = format_test_perf_bundle_default,
+ }
+#ifdef __x86_64__
+#define PERF_INTEL_CODE(event, umask) ((event) | (umask) << 8)
+ ,
+ {
+ .name = "core-power",
+ .desc =
+ "Core cycles where the core was running under specific turbo schedule.",
+ .type = PERF_TYPE_RAW,
+ .config[0] = PERF_INTEL_CODE (0x3c, 0x00),
+ .config[1] = PERF_INTEL_CODE (0x28, 0x07),
+ .config[2] = PERF_INTEL_CODE (0x28, 0x18),
+ .config[3] = PERF_INTEL_CODE (0x28, 0x20),
+ .config[4] = PERF_INTEL_CODE (0x28, 0x40),
+ .n_events = 5,
+ .format_fn = format_test_perf_bundle_core_power,
+ }
+#endif
+};