simulator bug and some YAMLs legacy field
authorimarom <[email protected]>
Thu, 11 Feb 2016 08:16:24 +0000 (03:16 -0500)
committerimarom <[email protected]>
Thu, 11 Feb 2016 08:16:24 +0000 (03:16 -0500)
scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
scripts/stl/yaml/imix_1pkt_vm.yaml
scripts/stl/yaml/imix_2pkt.yaml

index 71af88d..357f54b 100644 (file)
@@ -143,9 +143,9 @@ class STLSim(object):
             try:
                 profile = STLProfile.load(input_file)
             except STLError as e:
-                print format_text("\nError while loading profile '{0}'\n".format(input_file), 'bold')
-                print e.brief() + "\n"
-                return
+                s = format_text("\nError while loading profile '{0}'\n".format(input_file), 'bold')
+                s += "\n" + e.brief()
+                raise STLError(s)
 
             stream_list += profile.get_streams()
 
index 99f10ac..2260454 100644 (file)
@@ -4,7 +4,7 @@
   stream:
     self_start: True
     packet:
-      pcap: stl/udp_64B_no_crc.pcap  # pcap should not include CRC
+      pcap: udp_64B_no_crc.pcap  # pcap should not include CRC
     mode:
       type: continuous
       pps: 100
index 45f2303..406c28b 100644 (file)
@@ -4,19 +4,15 @@
   stream:
     self_start: True
     packet:
-      binary: stl/udp_64B_no_crc.pcap  # pcap should not include CRC
+      pcap: udp_64B_no_crc.pcap  # pcap should not include CRC
     mode:
       type: continuous
       pps: 100
-    rx_stats: []
-    vm: []
 - name: udp_594B
   stream:
     self_start: True
     packet:
-      binary: stl/udp_594B_no_crc.pcap  # pcap should not include CRC
+      pcap: udp_594B_no_crc.pcap  # pcap should not include CRC
     mode:
       type: continuous
       pps: 100
-    rx_stats: []
-    vm: []
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