revert mmain_dpdk.h commited by mistake code

add create config functional test
change order of cores in config file

diff --git a/scripts/automation/regression/functional_tests/trex_cfg_creator_test.py b/scripts/automation/regression/functional_tests/trex_cfg_creator_test.py
new file mode 100755 (executable)
index 0000000..ab6ab6f
--- /dev/null
+++ b/scripts/automation/regression/functional_tests/trex_cfg_creator_test.py
@@ -0,0 +1,698 @@
+#!/usr/bin/python 
+
+import sys
+import copy
+from collections import OrderedDict
+from trex import CTRexScenario
+sys.path.append(CTRexScenario.scripts_path)
+from dpdk_setup_ports import ConfigCreator, DpdkSetup
+sys.path.remove(CTRexScenario.scripts_path)
+from nose.tools import assert_raises
+import yaml
+
+class CompareLinesDiff(Exception): pass
+class CompareLinesNumDiff(Exception): pass
+class CompareTypeErr(Exception): pass
+
+def compare_lines(golden, output):
+    if type(golden) is not str:
+        raise CompareTypeErr('Type of golden should be str, got: %s' % type(golden))
+    if type(output) is not str:
+        raise CompareTypeErr('Type of output should be str, got: %s' % type(output))
+    golden_lines = golden.strip().splitlines()
+    output_lines = output.strip().splitlines()
+    if len(golden_lines) != len(output_lines):
+        raise CompareLinesNumDiff('Number of lines on golden is: %s, in output: %s\nGolden:\n%s\nGenerated:\n%s\n' % (len(golden_lines), len(output_lines), golden, output))
+    for line_num, (golden_line, output_line) in enumerate(zip(golden_lines, output_lines)):
+        if golden_line != output_line:
+            raise CompareLinesDiff('Produced YAML differs from golden at line %s.Golden: %s <-> Output: %s' % (line_num + 1, golden_line, output_line))
+
+def create_config(cpu_topology, interfaces, *args, **kwargs):
+    config = ConfigCreator(cpu_topology, interfaces, *args, **kwargs)
+    return config.create_config()
+
+def verify_master_core0(output):
+    output_yaml = yaml.safe_load(output)
+    assert type(output_yaml) is list, 'Generated YAML should be list'
+    assert len(output_yaml) is 1, 'Generated YAML should be list with 1 element'
+    output_yaml = output_yaml[0]
+    assert 'platform' in output_yaml, 'Generated YAML has no platform section:\n%s' % output
+    assert 'master_thread_id' in output_yaml['platform'], 'Generated YAML does not specify master thread id:\n%s' % output
+    assert output_yaml['platform']['master_thread_id'] is 0, 'Master thread id should be 0 in generated YAML, got:%s' % output_yaml['platform']['master_thread_id']
+
+class TRexCfgCreator_Test:
+
+    def test_vm_cfg(self):
+        cpu_topology = {0: OrderedDict([i, [i]] for i in range(5))}
+        interfaces = [{'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 1968,
+  'Device_str': 'VMXNET3 Ethernet Controller',
+  'Driver_str': 'vmxnet3',
+  'Interface': 'ens192',
+  'Interface_argv': '0b:00.0',
+  'Module_str': 'igb_uio,vfio-pci,uio_pci_generic',
+  'NUMA': -1,
+  'PhySlot': '192',
+  'PhySlot_str': '192',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '07b0',
+  'SDevice_str': 'VMXNET3 Ethernet Controller',
+  'SVendor': '15ad',
+  'SVendor_str': 'VMware',
+  'Slot': '0000:0b:00.0',
+  'Slot_str': '0b:00.0',
+  'Vendor': 5549,
+  'Vendor_str': 'VMware',
+  'dest_mac': '00:0c:29:92:f1:ca',
+  'src_mac': '00:0c:29:92:f1:d4',
+  'loopback_dest': True},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 1968,
+  'Device_str': 'VMXNET3 Ethernet Controller',
+  'Driver_str': 'vmxnet3',
+  'Interface': 'ens160',
+  'Interface_argv': '03:00.0',
+  'Module_str': 'igb_uio,vfio-pci,uio_pci_generic',
+  'NUMA': -1,
+  'PhySlot': '160',
+  'PhySlot_str': '160',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '07b0',
+  'SDevice_str': 'VMXNET3 Ethernet Controller',
+  'SVendor': '15ad',
+  'SVendor_str': 'VMware',
+  'Slot': '0000:03:00.0',
+  'Slot_str': '03:00.0',
+  'Vendor': 5549,
+  'Vendor_str': 'VMware',
+  'dest_mac': '00:0c:29:92:f1:d4',
+  'src_mac': '00:0c:29:92:f1:ca'}]
+        golden = '''
+### Config file generated by dpdk_setup_ports.py ###
+
+- port_limit: 2
+  version: 2
+  interfaces: ['0b:00.0', '03:00.0']
+  port_info:
+      - dest_mac: [0x00, 0x0c, 0x29, 0x92, 0xf1, 0xca] # MAC OF LOOPBACK TO IT'S DUAL INTERFACE
+        src_mac:  [0x00, 0x0c, 0x29, 0x92, 0xf1, 0xd4]
+      - dest_mac: [0x00, 0x0c, 0x29, 0x92, 0xf1, 0xd4]
+        src_mac:  [0x00, 0x0c, 0x29, 0x92, 0xf1, 0xca]
+
+  platform:
+      master_thread_id: 0
+      latency_thread_id: 1
+      dual_if:
+        - socket: 0
+          threads: [2]
+'''
+        output = create_config(cpu_topology, interfaces)
+        verify_master_core0(output)
+        compare_lines(golden, output)
+        with assert_raises(CompareLinesNumDiff):
+            compare_lines('1' + golden, output)
+        output = create_config(cpu_topology, interfaces, exclude_lcores = [0])
+        with assert_raises(AssertionError):
+            verify_master_core0(output)
+        output = create_config(cpu_topology, interfaces, include_lcores = [1,2,3,4])
+        with assert_raises(AssertionError):
+            verify_master_core0(output)
+        output = create_config(cpu_topology, interfaces, include_lcores = [0,2,3,4])
+        verify_master_core0(output)
+        output = create_config(cpu_topology, interfaces, include_lcores = [0,2,3,4], exclude_lcores = [0])
+        with assert_raises(AssertionError):
+            verify_master_core0(output)
+
+    def test_trex08_cfg(self):
+        cpu_topology = OrderedDict([(0, OrderedDict([(0, [0, 16]), (1, [1, 17]), (2, [2, 18]), (3, [3, 19]), (4, [4, 20]), (5, [5, 21]), (6, [6, 22]), (7, [7, 23])])), (1, OrderedDict([(0, [8, 24]), (1, [9, 25]), (2, [10, 26]), (3, [11, 27]), (4, [12, 28]), (5, [13, 29]), (6, [14, 30]), (7, [15, 31])]))])
+        interfaces = [{'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0002',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.0',
+  'Slot_str': '02:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '02:00:02:00:00:00',
+  'src_mac': '01:00:01:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.1',
+  'Slot_str': '02:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '01:00:01:00:00:00',
+  'src_mac': '02:00:02:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:84:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 1,
+  'PhySlot': '0-8',
+  'PhySlot_str': '0-8',
+  'ProgIf': '20',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0002',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:84:00.0',
+  'Slot_str': '84:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '04:00:04:00:00:00',
+  'src_mac': '03:00:03:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:84:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 1,
+  'PhySlot': '0-8',
+  'PhySlot_str': '0-8',
+  'ProgIf': '20',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:84:00.1',
+  'Slot_str': '84:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '03:00:03:00:00:00',
+  'src_mac': '04:00:04:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '05:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-3',
+  'PhySlot_str': '0-3',
+  'ProgIf': '01',
+  'Rev': '02',
+  'Rev_str': '02',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:05:00.0',
+  'Slot_str': '05:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '06:00:06:00:00:00',
+  'src_mac': '05:00:05:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '05:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-3',
+  'PhySlot_str': '0-3',
+  'ProgIf': '01',
+  'Rev': '02',
+  'Rev_str': '02',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:05:00.1',
+  'Slot_str': '05:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '05:00:05:00:00:00',
+  'src_mac': '06:00:06:00:00:00'}]
+        golden = '''
+### Config file generated by dpdk_setup_ports.py ###
+
+- port_limit: 6
+  version: 2
+  interfaces: ['02:00.0', '02:00.1', '84:00.0', '84:00.1', '05:00.0', '05:00.1']
+  port_bandwidth_gb: 40
+  port_info:
+      - dest_mac: [0x02, 0x00, 0x02, 0x00, 0x00, 0x00]
+        src_mac:  [0x01, 0x00, 0x01, 0x00, 0x00, 0x00]
+      - dest_mac: [0x01, 0x00, 0x01, 0x00, 0x00, 0x00]
+        src_mac:  [0x02, 0x00, 0x02, 0x00, 0x00, 0x00]
+
+      - dest_mac: [0x04, 0x00, 0x04, 0x00, 0x00, 0x00]
+        src_mac:  [0x03, 0x00, 0x03, 0x00, 0x00, 0x00]
+      - dest_mac: [0x03, 0x00, 0x03, 0x00, 0x00, 0x00]
+        src_mac:  [0x04, 0x00, 0x04, 0x00, 0x00, 0x00]
+
+      - dest_mac: [0x06, 0x00, 0x06, 0x00, 0x00, 0x00]
+        src_mac:  [0x05, 0x00, 0x05, 0x00, 0x00, 0x00]
+      - dest_mac: [0x05, 0x00, 0x05, 0x00, 0x00, 0x00]
+        src_mac:  [0x06, 0x00, 0x06, 0x00, 0x00, 0x00]
+
+  platform:
+      master_thread_id: 0
+      latency_thread_id: 16
+      dual_if:
+        - socket: 0
+          threads: [1,17,2,18,3,19,4]
+
+        - socket: 1
+          threads: [8,24,9,25,10,26,11]
+
+        - socket: 0
+          threads: [20,5,21,6,22,7,23]
+'''
+        output = create_config(cpu_topology, interfaces)
+        verify_master_core0(output)
+        compare_lines(golden, output)
+
+        interfaces = [{'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0002',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.0',
+  'Slot_str': '02:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '02:00:02:00:00:00',
+  'src_mac': '01:00:01:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.1',
+  'Slot_str': '02:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '01:00:01:00:00:00',
+  'src_mac': '02:00:02:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:84:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 1,
+  'PhySlot': '0-8',
+  'PhySlot_str': '0-8',
+  'ProgIf': '20',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0002',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:84:00.0',
+  'Slot_str': '84:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '04:00:04:00:00:00',
+  'src_mac': '03:00:03:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:84:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 1,
+  'PhySlot': '0-8',
+  'PhySlot_str': '0-8',
+  'ProgIf': '20',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:84:00.1',
+  'Slot_str': '84:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '03:00:03:00:00:00',
+  'src_mac': '04:00:04:00:00:00'}]
+        golden = '''
+### Config file generated by dpdk_setup_ports.py ###
+
+- port_limit: 4
+  version: 2
+  interfaces: ['02:00.0', '02:00.1', '84:00.0', '84:00.1']
+  port_bandwidth_gb: 40
+  port_info:
+      - dest_mac: [0x02, 0x00, 0x02, 0x00, 0x00, 0x00]
+        src_mac:  [0x01, 0x00, 0x01, 0x00, 0x00, 0x00]
+      - dest_mac: [0x01, 0x00, 0x01, 0x00, 0x00, 0x00]
+        src_mac:  [0x02, 0x00, 0x02, 0x00, 0x00, 0x00]
+
+      - dest_mac: [0x04, 0x00, 0x04, 0x00, 0x00, 0x00]
+        src_mac:  [0x03, 0x00, 0x03, 0x00, 0x00, 0x00]
+      - dest_mac: [0x03, 0x00, 0x03, 0x00, 0x00, 0x00]
+        src_mac:  [0x04, 0x00, 0x04, 0x00, 0x00, 0x00]
+
+  platform:
+      master_thread_id: 0
+      latency_thread_id: 31
+      dual_if:
+        - socket: 0
+          threads: [1,17,2,18,3,19,4,20,5,21,6,22,7,23,16]
+
+        - socket: 1
+          threads: [8,24,9,25,10,26,11,27,12,28,13,29,14,30,15]
+'''
+        output = create_config(cpu_topology, interfaces)
+        verify_master_core0(output)
+        compare_lines(golden, output)
+
+        interfaces = [{'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0002',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.0',
+  'Slot_str': '02:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '02:00:02:00:00:00',
+  'src_mac': '01:00:01:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.1',
+  'Slot_str': '02:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '01:00:01:00:00:00',
+  'src_mac': '02:00:02:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '05:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-3',
+  'PhySlot_str': '0-3',
+  'ProgIf': '01',
+  'Rev': '02',
+  'Rev_str': '02',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:05:00.0',
+  'Slot_str': '05:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '04:00:04:00:00:00',
+  'src_mac': '03:00:03:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '05:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-3',
+  'PhySlot_str': '0-3',
+  'ProgIf': '01',
+  'Rev': '02',
+  'Rev_str': '02',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:05:00.1',
+  'Slot_str': '05:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '03:00:03:00:00:00',
+  'src_mac': '04:00:04:00:00:00'}]
+        golden = '''
+### Config file generated by dpdk_setup_ports.py ###
+
+- port_limit: 4
+  version: 2
+  interfaces: ['02:00.0', '02:00.1', '05:00.0', '05:00.1']
+  port_bandwidth_gb: 40
+  port_info:
+      - dest_mac: [0x02, 0x00, 0x02, 0x00, 0x00, 0x00]
+        src_mac:  [0x01, 0x00, 0x01, 0x00, 0x00, 0x00]
+      - dest_mac: [0x01, 0x00, 0x01, 0x00, 0x00, 0x00]
+        src_mac:  [0x02, 0x00, 0x02, 0x00, 0x00, 0x00]
+
+      - dest_mac: [0x04, 0x00, 0x04, 0x00, 0x00, 0x00]
+        src_mac:  [0x03, 0x00, 0x03, 0x00, 0x00, 0x00]
+      - dest_mac: [0x03, 0x00, 0x03, 0x00, 0x00, 0x00]
+        src_mac:  [0x04, 0x00, 0x04, 0x00, 0x00, 0x00]
+
+  platform:
+      master_thread_id: 0
+      latency_thread_id: 16
+      dual_if:
+        - socket: 0
+          threads: [1,17,2,18,3,19,4]
+
+        - socket: 0
+          threads: [20,5,21,6,22,7,23]
+'''
+        output = create_config(cpu_topology, interfaces)
+        verify_master_core0(output)
+        compare_lines(golden, output)
+
+    def test_cfg_negative(self):
+        cpu_topology = OrderedDict([(0, OrderedDict([(0, [0, 16]), (1, [1, 17]), (2, [2, 18]), (3, [3, 19]), (4, [4, 20]), (5, [5, 21]), (6, [6, 22]), (7, [7, 23])])), (1, OrderedDict([(0, [8, 24]), (1, [9, 25]), (2, [10, 26]), (3, [11, 27]), (4, [12, 28]), (5, [13, 29]), (6, [14, 30]), (7, [15, 31])]))])
+        interfaces = [{'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.0',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0002',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.0',
+  'Slot_str': '02:00.0',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '02:00:02:00:00:00',
+  'src_mac': '01:00:01:00:00:00'},
+ {'Active': '',
+  'Class': '0200',
+  'Class_str': 'Ethernet controller',
+  'Device': 5507,
+  'Device_str': 'Ethernet Controller XL710 for 40GbE QSFP+',
+  'Driver_str': 'igb_uio',
+  'Interface': '',
+  'Interface_argv': '0000:02:00.1',
+  'Module_str': 'vfio-pci,uio_pci_generic',
+  'NUMA': 0,
+  'PhySlot': '0-1',
+  'PhySlot_str': '0-1',
+  'ProgIf': '01',
+  'Rev': '01',
+  'Rev_str': '01',
+  'SDevice': '0000',
+  'SDevice_str': 'Ethernet Converged Network Adapter XL710-Q2',
+  'SVendor': '8086',
+  'SVendor_str': 'Intel Corporation',
+  'Slot': '0000:02:00.1',
+  'Slot_str': '02:00.1',
+  'Vendor': 32902,
+  'Vendor_str': 'Intel Corporation',
+  'dest_mac': '01:00:01:00:00:00',
+  'src_mac': '02:00:02:00:00:00'}]
+        # types errors
+        with assert_raises(AssertionError):
+            create_config(None, None)
+        with assert_raises(AssertionError):
+            create_config(cpu_topology, None)
+        with assert_raises(AssertionError):
+            create_config(None, interfaces)
+        with assert_raises(AssertionError):
+            create_config(cpu_topology, [])
+        with assert_raises(AssertionError):
+            create_config({}, interfaces)
+        with assert_raises(AssertionError):
+            create_config({}, [])
+        # not enough cores at NUMA 0
+        with assert_raises(DpdkSetup):
+            create_config({0:{0:[]}, 1:{0:[1,2,3,4,5,6,7]}}, interfaces)
+        with assert_raises(DpdkSetup):
+            create_config({0:{0:[1]}, 1:{0:[3]}}, interfaces)
+        with assert_raises(DpdkSetup):
+            create_config({0:{0:[1,2]}}, interfaces)
+        # no NUMA 0 info, NICs at NUMA 0
+        cpu_topo1 = copy.deepcopy(cpu_topology)
+        del cpu_topo1[0]
+        with assert_raises(KeyError):
+            create_config(cpu_topo1, interfaces)
+        int1 = copy.deepcopy(interfaces)
+        for interface in int1:
+            interface['NUMA'] = 1
+        # now should work, as interfaces use NUMA 1
+        create_config(cpu_topo1, int1)
+        int2 = copy.deepcopy(interfaces)
+        int2[1]['NUMA'] = 1
+        # interfaces on different NUMAs
+        with assert_raises(DpdkSetup):
+            create_config(cpu_topology, int2)
+
+
+    def test_inner_comparator(self):
+        compare_lines('', '')
+        compare_lines('one\ntwo', 'one\ntwo')
+        with assert_raises(CompareLinesNumDiff):
+            compare_lines('one\ntwo', 'one\ntwo\nthree')
+        with assert_raises(CompareLinesDiff):
+            compare_lines('one\ntwo', 'one\ntwo1')
+        with assert_raises(CompareLinesDiff):
+            compare_lines('one\ntwo', 'one\nthree')
+        with assert_raises(CompareTypeErr):
+            compare_lines(None, 'one\nthree')
+        with assert_raises(CompareTypeErr):
+            compare_lines('one\ntwo', None)
+        with assert_raises(CompareTypeErr):
+            compare_lines(None, None)
+
+    @classmethod
+    def tearDownClass(cls):
+        sys.path.remove(CTRexScenario.scripts_path)
+        del sys.modules['dpdk_setup_ports']

diff --git a/scripts/dpdk_nic_bind.py b/scripts/dpdk_nic_bind.py
index a2c8e19..13806fd 100755 (executable)
--- a/scripts/dpdk_nic_bind.py
+++ b/scripts/dpdk_nic_bind.py
@@ -35,8 +35,10 @@
 import sys, os, getopt, subprocess, shlex
 from os.path import exists, abspath, dirname, basename
 from distutils.util import strtobool
-sys.path.append(os.path.join('external_libs', 'texttable-0.8.4'))
+text_tables_path = os.path.join('external_libs', 'texttable-0.8.4')
+sys.path.append(text_tables_path)
 import texttable
+sys.path.remove(text_tables_path)
 import re
 
 # The PCI device class for ETHERNET devices
@@ -506,7 +508,7 @@ def get_macs_from_trex(pci_addr_list):
             print("Could not run TRex to get MAC info about interfaces, check if it's already running.")
         else:
             print('Error upon running TRex to get MAC info:\n%s.' % stdout)
-        return {}
+        sys.exit(1)
     pci_mac_str = 'PCI: (\S+).+?MAC: (\S+)'
     pci_mac_re = re.compile(pci_mac_str)
     for line in stdout.splitlines():

diff --git a/scripts/dpdk_setup_ports.py b/scripts/dpdk_setup_ports.py
index 3ab13a2..e996010 100755 (executable)
--- a/scripts/dpdk_setup_ports.py
+++ b/scripts/dpdk_setup_ports.py
@@ -41,7 +41,7 @@ class ConfigCreator(object):
         include_lcores = [int(x) for x in include_lcores]
         exclude_lcores = [int(x) for x in exclude_lcores]
         self.has_zero_lcore = False
-        for cores in self.cpu_topology.values():
+        for numa, cores in self.cpu_topology.items():
             for core, lcores in cores.items():
                 for lcore in copy.copy(lcores):
                     if include_lcores and lcore not in include_lcores:
@@ -51,6 +51,12 @@ class ConfigCreator(object):
                 if 0 in lcores:
                     self.has_zero_lcore = True
                     cores[core].remove(0)
+                    zero_lcore_numa = numa
+                    zero_lcore_core = core
+                    zero_lcore_siblings = cores[core]
+        if self.has_zero_lcore:
+            del self.cpu_topology[zero_lcore_numa][zero_lcore_core]
+            self.cpu_topology[zero_lcore_numa][zero_lcore_core] = zero_lcore_siblings
         Device_str = None
         for interface in self.interfaces:
             for mandatory_interface_field in ConfigCreator.mandatory_interface_fields:
@@ -108,18 +114,24 @@ class ConfigCreator(object):
         if self.zmq_rpc_port:
             config_str += '  zmq_rpc_port: %s\n' % self.zmq_rpc_port
         config_str += '  port_info:\n'
-        for interface in self.interfaces:
-            config_str += ' '*6 + '- dest_mac: [%s]\n' % self._convert_mac(interface['dest_mac'])
+        for index, interface in enumerate(self.interfaces):
+            config_str += ' '*6 + '- dest_mac: [%s]' % self._convert_mac(interface['dest_mac'])
+            if interface.get('loopback_dest'):
+                config_str += " # MAC OF LOOPBACK TO IT'S DUAL INTERFACE\n"
+            else:
+                config_str += '\n'
             config_str += ' '*8 + 'src_mac:  [%s]\n' % self._convert_mac(interface['src_mac'])
-        config_str += '\n  platform:\n'
+            if index % 2:
+                config_str += '\n' # dual if barrier
+        config_str += '  platform:\n'
         if len(self.interfaces_per_numa.keys()) == 1 and -1 in self.interfaces_per_numa: # VM, use any cores, 1 core per dual_if
             lcores_pool = sorted([lcore for lcores in self.lcores_per_numa.values() for lcore in lcores])
             config_str += ' '*6 + 'master_thread_id: %s\n' % (0 if self.has_zero_lcore else lcores_pool.pop())
-            config_str += ' '*6 + 'latency_thread_id: %s\n' % lcores_pool.pop()
+            config_str += ' '*6 + 'latency_thread_id: %s\n' % lcores_pool.pop(0)
             config_str += ' '*6 + 'dual_if:\n'
             for i in range(0, len(self.interfaces), 2):
                 config_str += ' '*8 + '- socket: 0\n'
-                config_str += ' '*10 + 'threads: [%s]\n\n' % lcores_pool.pop()
+                config_str += ' '*10 + 'threads: [%s]\n\n' % lcores_pool.pop(0)
         else:
             # we will take common minimum among all NUMAs, to satisfy all
             lcores_per_dual_if = 99
@@ -137,14 +149,14 @@ class ConfigCreator(object):
             for i in range(0, len(self.interfaces), 2):
                 numa = self.interfaces[i]['NUMA']
                 dual_if_section += ' '*8 + '- socket: %s\n' % numa
-                lcores_for_this_dual_if = [str(lcores_pool[numa].pop()) for _ in range(lcores_per_dual_if)]
+                lcores_for_this_dual_if = [str(lcores_pool[numa].pop(0)) for _ in range(lcores_per_dual_if)]
                 if not lcores_for_this_dual_if:
                     raise DpdkSetup('Not enough cores at NUMA %s. This NUMA has %s processing units and %s interfaces.' % (numa, len(self.lcores_per_numa[numa]), self.interfaces_per_numa[numa]))
                 dual_if_section += ' '*10 + 'threads: [%s]\n\n' % ','.join(lcores_for_this_dual_if)
             # take the cores left to master and rx
             lcores_pool_left = [lcore for lcores in lcores_pool.values() for lcore in lcores]
-            config_str += ' '*6 + 'master_thread_id: %s\n' % (0 if self.has_zero_lcore else lcores_pool_left.pop())
-            config_str += ' '*6 + 'latency_thread_id: %s\n' % lcores_pool_left.pop()
+            config_str += ' '*6 + 'master_thread_id: %s\n' % (0 if self.has_zero_lcore else lcores_pool_left.pop(0))
+            config_str += ' '*6 + 'latency_thread_id: %s\n' % lcores_pool_left.pop(0)
             # add the dual_if section
             config_str += dual_if_section
 
@@ -358,6 +370,7 @@ Other network devices
             dual_index = i + 1 - (i % 2) * 2
             if 'dest_mac' not in wanted_interfaces[dual_index]:
                 wanted_interfaces[dual_index]['dest_mac'] = interface['MAC'] # loopback
+                wanted_interfaces[dual_index]['loopback_dest'] = True
 
         cpu_topology_file = '/proc/cpuinfo'
         # physical processor -> physical core -> logical processing units (threads)
@@ -401,12 +414,18 @@ Examples:
 To unbind the interfaces using the trex configuration file 
   sudo ./dpdk_set_ports.py -l
 
-To create a default config file 
+To create a default config file (example1)
   sudo ./dpdk_setup_ports.py -c 02:00.0 02:00.1 -o /etc/trex_cfg.yaml
 
+To create a default config file (example2)
+  sudo ./dpdk_setup_ports.py -c eth1 eth2 --dest-macs 11:11:11:11:11:11 22:22:22:22:22:22 --dump
+
 To show interfaces status
   sudo ./dpdk_set_ports.py -s
 
+To see more detailed info on interfaces (table):
+  sudo ./dpdk_set_ports.py -t
+
     """,
     description=" unbind dpdk interfaces ",
     epilog=" written by hhaim");
@@ -472,7 +491,7 @@ To show interfaces status
      )
 
     parser.add_argument('--version', action='version',
-                        version="0.1" )
+                        version="0.2" )
 
     map_driver.args = parser.parse_args();
     if map_driver.args.parent :

diff --git a/src/main_dpdk.h b/src/main_dpdk.h
index 935a27e..3104ff5 100644 (file)
--- a/src/main_dpdk.h
+++ b/src/main_dpdk.h
@@ -122,8 +122,10 @@ class CPhyEthIF  {
     }
     void flush_dp_rx_queue(void);
     void flush_rx_queue(void);
-    int add_rx_flow_stat_rule(uint8_t type, uint16_t proto, uint16_t id);
-    int del_rx_flow_stat_rule(uint8_t type, uint16_t proto, uint16_t id);
+    int add_rx_flow_stat_rule(uint8_t port_id, uint16_t l3_type, uint8_t l4_proto
+                          , uint8_t ipv6_next_h, uint16_t id) const;
+    int del_rx_flow_stat_rule(uint8_t port_id, uint16_t l3_type, uint8_t l4_proto
+                          , uint8_t ipv6_next_h, uint16_t id) const;
     inline uint16_t  tx_burst(uint16_t queue_id, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) {
         return rte_eth_tx_burst(m_port_id, queue_id, tx_pkts, nb_pkts);
     }