Type: improvement
In certain use cases, the underlying pools expand by allocating a new,
larger pool and copying the existing elements into it. This process
can be time-consuming, leading to slower control plane configurations,
especially when a large number of elements are already present.
This patch allows users to pre-configure some of these pools through
startup.conf.
It also fixes alignment for ip4 mtrie.
Signed-off-by: Mohsin Kazmi <[email protected]>
Signed-off-by: BenoƮt Ganne <[email protected]>
Change-Id: Ib0f1d40e3efb8b4fce989219196c718d6834498a
* This should never be used, but just in case, stack it on a drop.
*/
lbi = load_balance_create(1, DPO_PROTO_IP4, 0);
+ ASSERT(0 == lbi);
load_balance_set_bucket(lbi, 0, drop_dpo_get(DPO_PROTO_IP4));
load_balance_logger =
load_balance_map_module_init();
}
+void
+load_balance_pool_alloc (uword size)
+{
+ pool_alloc_aligned(load_balance_pool, size, CLIB_CACHE_LINE_BYTES);
+}
+
static clib_error_t *
load_balance_show (vlib_main_t * vm,
unformat_input_t * input,
}
extern void load_balance_module_init(void);
+extern void load_balance_pool_alloc (uword size);
#endif
fib_entry_track_module_init();
}
+void
+fib_entry_pool_alloc (uword size)
+{
+ pool_alloc(fib_entry_pool, size);
+}
+
fib_route_path_t *
fib_entry_encode (fib_node_index_t fib_entry_index)
{
flow_hash_config_t hash_config);
extern void fib_entry_module_init(void);
+extern void fib_entry_pool_alloc(uword size);
extern u32 fib_entry_get_stats_index(fib_node_index_t fib_entry_index);
{
ip4_mtrie_8_ply_t *root;
- pool_get (ip4_ply_pool, root);
+ pool_get_aligned (ip4_ply_pool, root, CLIB_CACHE_LINE_BYTES);
m->root_ply = root - ip4_ply_pool;
ply_8_init (root, IP4_MTRIE_LEAF_EMPTY, 0, 0);
clib_error_t *error = NULL;
/* Burn one ply so index 0 is taken */
- pool_get (ip4_ply_pool, p);
+ pool_get_aligned (ip4_ply_pool, p, CLIB_CACHE_LINE_BYTES);
return (error);
}
VLIB_INIT_FUNCTION (ip4_mtrie_module_init);
+void
+ip4_mtrie_pool_alloc (uword size)
+{
+ pool_alloc_aligned (ip4_ply_pool, size, CLIB_CACHE_LINE_BYTES);
+}
+
/*
* fd.io coding-style-patch-verification: ON
*
*/
extern ip4_mtrie_8_ply_t *ip4_ply_pool;
+/**
+ * @brief Pre-allocate the pool of plys
+ */
+extern void ip4_mtrie_pool_alloc (uword size);
+
/**
* Is the leaf terminal (i.e. an LB index) or non-terminal (i.e. a PLY index)
*/
*/
#include <vnet/ip/ip.h>
+#include <vnet/ip/ip4_mtrie.h>
+#include <vnet/fib/fib_entry.h>
+#include <vnet/dpo/load_balance.h>
ip_main_t ip_main;
"flow_classify_init"),
};
+static clib_error_t *
+ip_config_init (vlib_main_t *vm, unformat_input_t *input)
+{
+ uword lbsz = 0, fibentrysz = 0, mtriesz = 0;
+
+ while (unformat_check_input (input) != UNFORMAT_END_OF_INPUT)
+ {
+ if (unformat (input, "load-balance-pool-size %U", unformat_memory_size,
+ &lbsz))
+ ;
+ else if (unformat (input, "fib-entry-pool-size %U", unformat_memory_size,
+ &fibentrysz))
+ ;
+ else if (unformat (input, "ip4-mtrie-pool-size %U", unformat_memory_size,
+ &mtriesz))
+ ;
+ else
+ return clib_error_return (0, "unknown input `%U'",
+ format_unformat_error, input);
+ }
+
+ if (lbsz)
+ load_balance_pool_alloc (lbsz);
+ if (fibentrysz)
+ fib_entry_pool_alloc (fibentrysz);
+ if (mtriesz)
+ ip4_mtrie_pool_alloc (mtriesz);
+
+ return 0;
+}
+
+VLIB_CONFIG_FUNCTION (ip_config_init, "l3fib");
+
/*
* fd.io coding-style-patch-verification: ON
*
# update-interval <f64-seconds>, sets the segment scrape / update interval
# }
+## L3 FIB
+# l3fib {
+ ## load balance pool size preallocation (expected number of objects)
+ # load-balance-pool-size 1M
+
+ ## fib entry pool size preallocation (expected number of objects)
+ # fib-entry-pool-size 1M
+
+ ## ip4 mtrie pool size preallocation (expected number of mtries)
+ # ip4-mtrie-pool-size 1K
+# }
+
## L2 FIB
# l2fib {
## l2fib hash table size.