simulator breakage fix

diff --git a/scripts/automation/trex_control_plane/stl/console/trex_tui.py b/scripts/automation/trex_control_plane/stl/console/trex_tui.py
index 0a3d1a6..6dff0a6 100644 (file)
--- a/scripts/automation/trex_control_plane/stl/console/trex_tui.py
+++ b/scripts/automation/trex_control_plane/stl/console/trex_tui.py
@@ -600,8 +600,6 @@ class TrexTUI():
                 if status == AsyncKeys.STATUS_NONE:
                     time.sleep(0.001)
 
-                if self.tui_global_lock.locked():
-                    self.x += 1
                 with self.tui_global_lock:
                     self.handle_state_machine()
 

diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py
index 2074080..890ce7d 100644 (file)
--- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py
+++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py
@@ -710,7 +710,7 @@ class Port(object):
                                      ('L2 len',       len(obj['pkt']) + 4),
                                      ('mode',         obj['mode']),
                                      ('rate',         obj['rate']),
-                                     ('next_stream',  obj['next_id'])
+                                     ('next_stream',  obj['next_id'] if not '-1' else 'None')
                                     ])
     
         return {"streams" : OrderedDict(sorted(data.items())) }

diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
index 62724e6..3e63c4e 100644 (file)
--- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
+++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
@@ -40,6 +40,8 @@ class BpSimException(Exception):
 
 # stateless simulation
 class STLSim(object):
+    MASK_ALL = ((1 << 64) - 1)
+
     def __init__ (self, bp_sim_path, handler = 0, port_id = 0, api_h = "dummy"):
 
         self.bp_sim_path = os.path.abspath(bp_sim_path)
@@ -61,7 +63,8 @@ class STLSim(object):
                             "force":  force,
                             "port_id": self.port_id,
                             "mul": parsing_opts.decode_multiplier(mult),
-                            "duration": duration}
+                            "duration": duration,
+                            "core_mask": self.MASK_ALL}
                  }
 
 

diff --git a/src/sim/trex_sim_stateless.cpp b/src/sim/trex_sim_stateless.cpp
index 20041c2..6d47070 100644 (file)
--- a/src/sim/trex_sim_stateless.cpp
+++ b/src/sim/trex_sim_stateless.cpp
@@ -246,6 +246,7 @@ void
 SimStateless::prepare_dataplane() {
     
     CGlobalInfo::m_options.m_expected_portd = m_port_count;
+    CGlobalInfo::m_options.m_run_mode = CParserOption::RUN_MODE_INTERACTIVE;
 
     assert(CMsgIns::Ins()->Create(m_dp_core_count));
     m_fl.Create();