l2: fix latency issue casued by unnecesary read of previous cacheline

In majority of cases ethernet header sits at the beggining of cacheline.
Reading (dst_mac - 2) into 64 bit register is much more expensive
than doing simple bitwise shift, specially if previous cacheline is
not prefetched.

Change-Id: I35e53eae735098fb917a87c307e60a87e76e460f
Signed-off-by: Damjan Marion <damarion@cisco.com>

diff --git a/vnet/vnet/l2/l2_fib.h b/vnet/vnet/l2/l2_fib.h
index 8e7a52e..63f394c 100644 (file)
--- a/vnet/vnet/l2/l2_fib.h
+++ b/vnet/vnet/l2/l2_fib.h
@@ -105,7 +105,7 @@ l2fib_make_key (u8 * mac_address, u16 bd_index)
    * Create the in-register key as F:E:D:C:B:A:H:L
    * In memory the key is L:H:A:B:C:D:E:F
    */
-  temp = *((u64 *) (mac_address - 2));
+  temp = *((u64 *) (mac_address)) << 16;
   temp = (temp & ~0xffff) | (u64) (bd_index);
 #else
   /*