octeon: set cpt descriptor count to 16k 56/42356/4
authorNithinsen Kaithakadan <nkaithakadan@marvell.com>
Thu, 23 Jan 2025 05:04:52 +0000 (10:34 +0530)
committerDamjan Marion <dmarion@0xa5.net>
Tue, 1 Apr 2025 14:21:00 +0000 (14:21 +0000)
Set the number of CPT descriptors to 16384.
Add an option to configure cpt descriptor count
from startup conf.

Type: feature

Signed-off-by: Nithinsen Kaithakadan <nkaithakadan@marvell.com>
Change-Id: Id1ffbe69ad7d457dbd0b11494be1dc0d4a28c324

src/plugins/dev_octeon/crypto.c
src/plugins/dev_octeon/crypto.h
src/plugins/dev_octeon/init.c
src/plugins/dev_octeon/octeon.h

index cc0b073..52c7960 100644 (file)
@@ -1940,7 +1940,7 @@ oct_init_crypto_engine_handlers (vlib_main_t *vm, vnet_dev_t *dev)
 }
 
 int
-oct_conf_sw_queue (vlib_main_t *vm, vnet_dev_t *dev)
+oct_conf_sw_queue (vlib_main_t *vm, vnet_dev_t *dev, oct_crypto_dev_t *ocd)
 {
   oct_crypto_main_t *ocm = &oct_crypto_main;
   vlib_thread_main_t *tm = vlib_get_thread_main ();
@@ -1961,7 +1961,7 @@ oct_conf_sw_queue (vlib_main_t *vm, vnet_dev_t *dev)
    * Each pending queue will get number of cpt desc / number of cores.
    * And that desc count is shared across inflight entries.
    */
-  n_inflight_req = (OCT_CPT_LF_MAX_NB_DESC / tm->n_vlib_mains);
+  n_inflight_req = (ocd->n_desc / tm->n_vlib_mains);
 
   for (i = 0; i < tm->n_vlib_mains; ++i)
     {
index 5bd26f6..4d8c56a 100644 (file)
@@ -11,6 +11,9 @@
 
 #define OCT_MAX_N_CPT_DEV 2
 
+#define OCT_CPT_LF_DEF_NB_DESC 16384
+
+#define OCT_CPT_LF_MIN_NB_DESC 1024
 #define OCT_CPT_LF_MAX_NB_DESC 128000
 
 /* CRYPTO_ID, KEY_LENGTH_IN_BYTES, TAG_LEN, AAD_LEN */
@@ -81,6 +84,7 @@ typedef struct
   struct roc_cpt_lmtline lmtline;
   struct roc_cpt_lf lf;
   vnet_dev_t *dev;
+  u32 n_desc;
 } oct_crypto_dev_t;
 
 typedef struct
@@ -211,5 +215,6 @@ vnet_crypto_async_frame_t *oct_crypto_frame_dequeue (vlib_main_t *vm,
                                                     u32 *nb_elts_processed,
                                                     u32 *enqueue_thread_idx);
 int oct_init_crypto_engine_handlers (vlib_main_t *vm, vnet_dev_t *dev);
-int oct_conf_sw_queue (vlib_main_t *vm, vnet_dev_t *dev);
+int oct_conf_sw_queue (vlib_main_t *vm, vnet_dev_t *dev,
+                      oct_crypto_dev_t *ocd);
 #endif /* _CRYPTO_H_ */
index 561cbe9..69fb097 100644 (file)
@@ -61,6 +61,22 @@ static struct
 #undef _
 };
 
+static vnet_dev_arg_t oct_dev_args[] = {
+  {
+    .id = OCT_DEV_ARG_CRYPTO_N_DESC,
+    .name = "n_desc",
+    .desc = "number of cpt descriptors, applicable to cpt devices only",
+    .type = VNET_DEV_ARG_TYPE_UINT32,
+    .default_val.uint32 = OCT_CPT_LF_DEF_NB_DESC,
+  },
+  {
+    .id = OCT_DEV_ARG_END,
+    .name = "end",
+    .desc = "Argument end",
+    .type = VNET_DEV_ARG_END,
+  },
+};
+
 static u8 *
 oct_probe (vlib_main_t *vm, vnet_dev_bus_index_t bus_index, void *dev_info)
 {
@@ -241,7 +257,7 @@ oct_conf_cpt_queue (vlib_main_t *vm, vnet_dev_t *dev, oct_crypto_dev_t *ocd)
   cpt_lf = &ocd->lf;
   cpt_lmtline = &ocd->lmtline;
 
-  cpt_lf->nb_desc = OCT_CPT_LF_MAX_NB_DESC;
+  cpt_lf->nb_desc = ocd->n_desc;
   cpt_lf->lf_id = 0;
   if ((rrv = roc_cpt_lf_init (roc_cpt, cpt_lf)) < 0)
     return cnx_return_roc_err (dev, rrv, "roc_cpt_lf_init");
@@ -261,6 +277,7 @@ oct_init_cpt (vlib_main_t *vm, vnet_dev_t *dev)
   extern oct_plt_init_param_t oct_plt_init_param;
   oct_device_t *cd = vnet_dev_get_data (dev);
   oct_crypto_dev_t *ocd = NULL;
+  u32 n_desc;
   int rrv;
 
   if (ocm->n_cpt == OCT_MAX_N_CPT_DEV || ocm->started)
@@ -274,6 +291,27 @@ oct_init_cpt (vlib_main_t *vm, vnet_dev_t *dev)
   ocd->roc_cpt->pci_dev = &cd->plt_pci_dev;
 
   ocd->dev = dev;
+  ocd->n_desc = OCT_CPT_LF_DEF_NB_DESC;
+
+  foreach_vnet_dev_args (arg, dev)
+    {
+      if (arg->id == OCT_DEV_ARG_CRYPTO_N_DESC &&
+         vnet_dev_arg_get_uint32 (arg))
+       {
+         n_desc = vnet_dev_arg_get_uint32 (arg);
+         if (n_desc < OCT_CPT_LF_MIN_NB_DESC ||
+             n_desc > OCT_CPT_LF_MAX_NB_DESC)
+           {
+             log_err (dev,
+                      "number of cpt descriptors should be within range "
+                      "of %u and %u",
+                      OCT_CPT_LF_MIN_NB_DESC, OCT_CPT_LF_MAX_NB_DESC);
+             return VNET_DEV_ERR_NOT_SUPPORTED;
+           }
+
+         ocd->n_desc = vnet_dev_arg_get_uint32 (arg);
+       }
+    }
 
   if ((rrv = roc_cpt_dev_init (ocd->roc_cpt)))
     return cnx_return_roc_err (dev, rrv, "roc_cpt_dev_init");
@@ -290,7 +328,7 @@ oct_init_cpt (vlib_main_t *vm, vnet_dev_t *dev)
        * Initialize s/w queues, which are common across multiple
        * crypto devices
        */
-      oct_conf_sw_queue (vm, dev);
+      oct_conf_sw_queue (vm, dev, ocd);
 
       ocm->crypto_dev[0] = ocd;
     }
@@ -396,6 +434,7 @@ VNET_DEV_REGISTER_DRIVER (octeon) = {
     .free = oct_free,
     .probe = oct_probe,
   },
+  .args = oct_dev_args,
 };
 
 static clib_error_t *
index ccf8f62..0cf9375 100644 (file)
 
 #define OCT_BATCH_ALLOC_IOVA0_MASK 0xFFFFFFFFFFFFFF80
 
+typedef enum
+{
+  OCT_DEV_ARG_CRYPTO_N_DESC = 1,
+  OCT_DEV_ARG_END,
+} oct_dev_args_t;
+
 typedef enum
 {
   OCT_DEVICE_TYPE_UNKNOWN = 0,