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Define cache line size for x86 32-bit 90/6390/2
authorDamjan Marion <damarion@cisco.com>
Mon, 24 Apr 2017 18:52:35 +0000 (20:52 +0200)
committerFlorin Coras <florin.coras@gmail.com>
Tue, 25 Apr 2017 00:08:57 +0000 (00:08 +0000)
Change-Id: Ie70e805f342bda69207b9df9543f1eccb5e69612
Signed-off-by: Damjan Marion <damarion@cisco.com>
src/vppinfra/cache.h patch | blob | history

diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index 8e1f948..7464b77 100644 (file)
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -45,7 +45,7 @@
  */
 #ifndef CLIB_LOG2_CACHE_LINE_BYTES
 
-#if defined(__x86_64__) || defined(__ARM_ARCH_7A__)
+#if defined(__x86_64__) || defined(__ARM_ARCH_7A__) || defined(__i386__)
 #define CLIB_LOG2_CACHE_LINE_BYTES 6
 #endif
 
Vector Packet Processing