From: Zhiyong Yang <zhiyong.yang@intel.com>
Date: Wed, 20 Mar 2019 07:35:39 +0000 (-0400)
Subject: dpdk_esp_encrypt: add to prefetch data
X-Git-Tag: v20.01-rc0~762
X-Git-Url: https://gerrit.fd.io/r/gitweb?a=commitdiff_plain;h=2c1904fa8efffabfadd7f09edb4da98c2e172cd6;p=vpp.git

dpdk_esp_encrypt: add to prefetch data

The memory areas storing vlib_buffer_t and ip4|6_and_esp_header_t
are not prefetched. The patch help dpdk_esp_encrypt to reduce 18
clocks/pkt from 149 to 131 on Haswell when running IPsec in tunnel
mode.

Change-Id: I4f4e9e2b3982a4b7810cab8ed828a5e4631f8f8c
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
---

diff --git a/src/plugins/dpdk/ipsec/esp_encrypt.c b/src/plugins/dpdk/ipsec/esp_encrypt.c
index 908f846e315..653c158fb94 100644
--- a/src/plugins/dpdk/ipsec/esp_encrypt.c
+++ b/src/plugins/dpdk/ipsec/esp_encrypt.c
@@ -155,8 +155,8 @@ dpdk_esp_encrypt_inline (vlib_main_t * vm,
       while (n_left_from > 0 && n_left_to_next > 0)
 	{
 	  clib_error_t *error;
-	  u32 bi0;
-	  vlib_buffer_t *b0 = 0;
+	  u32 bi0, bi1;
+	  vlib_buffer_t *b0, *b1;
 	  u32 sa_index0;
 	  ip4_and_esp_header_t *ih0, *oh0 = 0;
 	  ip6_and_esp_header_t *ih6_0, *oh6_0 = 0;
@@ -169,7 +169,7 @@ dpdk_esp_encrypt_inline (vlib_main_t * vm,
 	  u8 trunc_size;
 	  u16 rewrite_len;
 	  u16 udp_encap_adv = 0;
-	  struct rte_mbuf *mb0 = 0;
+	  struct rte_mbuf *mb0;
 	  struct rte_crypto_op *op;
 	  u16 res_idx;
 
@@ -188,6 +188,16 @@ dpdk_esp_encrypt_inline (vlib_main_t * vm,
 	  /* mb0 */
 	  CLIB_PREFETCH (mb0, CLIB_CACHE_LINE_BYTES, STORE);
 
+	  if (n_left_from > 1)
+	    {
+	      bi1 = from[1];
+	      b1 = vlib_get_buffer (vm, bi1);
+
+	      CLIB_PREFETCH (b1, CLIB_CACHE_LINE_BYTES, LOAD);
+	      CLIB_PREFETCH (b1->data - CLIB_CACHE_LINE_BYTES,
+			     CLIB_CACHE_LINE_BYTES, STORE);
+	    }
+
 	  op = ops[0];
 	  ops += 1;
 	  ASSERT (op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED);