From: Tianyu Li <tianyu.li@arm.com>
Date: Wed, 23 Jun 2021 07:35:03 +0000 (+0000)
Subject: vlib: fix buffer pool alignment size
X-Git-Tag: v22.02-rc0~233
X-Git-Url: https://gerrit.fd.io/r/gitweb?a=commitdiff_plain;h=70b1cbdf2bd7687f840a59475ca769c9bab907c9;p=vpp.git

vlib: fix buffer pool alignment size

Alignment size should be CLIB_CACHE_LINE_BYTES(64)
instead of CLIB_LOG2_CACHE_LINE_BYTES(6)

Type: fix

Signed-off-by: Tianyu Li <tianyu.li@arm.com>
Change-Id: If2d5ae324093be64454377866297f5e76ccddc93
---

diff --git a/src/vlib/buffer.c b/src/vlib/buffer.c
index ae88b4e4d44..adaafa36f5d 100644
--- a/src/vlib/buffer.c
+++ b/src/vlib/buffer.c
@@ -509,7 +509,7 @@ vlib_buffer_pool_create (vlib_main_t * vm, char *name, u32 data_size,
   if (vec_len (bm->buffer_pools) >= 255)
     return ~0;
 
-  vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_LOG2_CACHE_LINE_BYTES);
+  vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_CACHE_LINE_BYTES);
 
   if (bm->buffer_mem_size == 0)
     {