From: Ido Barnea <ibarnea@cisco.com>
Date: Wed, 5 Oct 2016 13:18:39 +0000 (+0300)
Subject: Fix issue with set_rcv_all in 1G
X-Git-Url: https://gerrit.fd.io/r/gitweb?a=commitdiff_plain;h=d62aeaa718739812c82e34e95405f3b640d76093;p=trex.git

Fix issue with set_rcv_all in 1G
---

diff --git a/src/main_dpdk.cpp b/src/main_dpdk.cpp
index edeeb3ee..480045f5 100644
--- a/src/main_dpdk.cpp
+++ b/src/main_dpdk.cpp
@@ -5543,16 +5543,17 @@ int CTRexExtendedDriverBase1G::set_rcv_all(CPhyEthIF * _if, bool set_on) {
 
     clear_rx_filter_rules(_if);
 
-    if (! set_on)
-        return 0;
-
-    for (int rule_id = 0; rule_id < sizeof(eth_types); rule_id++) {
-        mask |= 0x1 << rule_id;
-        // Filter for byte 12 of packet
-        _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 4) ,  0x000000 | eth_types[rule_id]);
-        _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 8) , 0x10); /* MASK */
-        // FLEX_PRIO[[18:16] = 1, RQUEUE[10:8] = 1, len = 24
-        _if->pci_reg_write( (E1000_FHFT(rule_id) + 0xFC) , (1 << 16) | (1 << 8) | 24);
+    if (set_on) {
+        for (int rule_id = 0; rule_id < sizeof(eth_types); rule_id++) {
+            mask |= 0x1 << rule_id;
+            // Filter for byte 12 of packet
+            _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 4) ,  0x000000 | eth_types[rule_id]);
+            _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 8) , 0x10); /* MASK */
+            // FLEX_PRIO[[18:16] = 1, RQUEUE[10:8] = 1, len = 24
+            _if->pci_reg_write( (E1000_FHFT(rule_id) + 0xFC) , (1 << 16) | (1 << 8) | 24);
+        }
+    } else {
+        configure_rx_filter_rules(_if);
     }
 
     return 0;