From: Marvin Liu <yong.liu@intel.com>
Date: Wed, 15 Mar 2023 15:00:52 +0000 (+0800)
Subject: dma_intel: fix potential invalid batch status
X-Git-Tag: v23.10-rc0~136
X-Git-Url: https://gerrit.fd.io/r/gitweb?a=commitdiff_plain;h=refs%2Fchanges%2F88%2F38488%2F1;p=vpp.git

dma_intel: fix potential invalid batch status

DMA batch status was set by hardware. Its value may be variable between
cpus twice accesses. Saving the value of status can fix it.

Type: fix

Signed-off-by: Marvin Liu <yong.liu@intel.com>
Change-Id: Ibc9337239555744a571685b486c986991c3e9b18
---

diff --git a/src/plugins/dma_intel/dsa.c b/src/plugins/dma_intel/dsa.c
index a1efcfaa42a..473f2efa93e 100644
--- a/src/plugins/dma_intel/dsa.c
+++ b/src/plugins/dma_intel/dsa.c
@@ -350,7 +350,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
   intel_dsa_thread_t *t =
     vec_elt_at_index (idm->dsa_threads, vm->thread_index);
   u32 n_pending = 0, n = 0;
-  u8 glitch = 0;
+  u8 glitch = 0, status;
 
   if (!t->pending_batches)
     return 0;
@@ -362,8 +362,9 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
       intel_dsa_batch_t *b = t->pending_batches[i];
       intel_dsa_channel_t *ch = b->ch;
 
-      if ((b->status == INTEL_DSA_STATUS_SUCCESS ||
-	   b->status == INTEL_DSA_STATUS_CPU_SUCCESS) &&
+      status = b->status;
+      if ((status == INTEL_DSA_STATUS_SUCCESS ||
+	   status == INTEL_DSA_STATUS_CPU_SUCCESS) &&
 	  !glitch)
 	{
 	  /* callback */
@@ -384,7 +385,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
 	  vec_add1 (idm->dsa_config_heap[b->config_heap_index].freelist, b);
 
 	  intel_dsa_channel_lock (ch);
-	  if (b->status == INTEL_DSA_STATUS_SUCCESS)
+	  if (status == INTEL_DSA_STATUS_SUCCESS)
 	    {
 	      ch->n_enq--;
 	      ch->completed++;
@@ -396,7 +397,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
 	  b->batch.n_enq = 0;
 	  b->status = INTEL_DSA_STATUS_IDLE;
 	}
-      else if (b->status == INTEL_DSA_STATUS_BUSY)
+      else if (status == INTEL_DSA_STATUS_BUSY)
 	{
 	  glitch = 1 & b->barrier_before_last;
 	  t->pending_batches[n++] = b;