docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst

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  30
  31 IPSec IPv4 Routing
  32 ==================
  33
  34 Following sections include Throughput Speedup Analysis for VPP multi-
  35 core multi-thread configurations with no Hyper-Threading, specifically
  36 for tested 2t2c (2threads, 2cores) and 4t4c scenarios. 1t1c throughput
  37 results are used as a reference for reported speedup ratio.
  38 VPP IPSec encryption is accelerated using DPDK cryptodev
  39 library driving Intel Quick Assist (QAT) crypto PCIe hardware cards.
  40 Performance is reported for VPP running in multiple configurations of
  41 VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
  42 physical CPU core(s) placement.
  43
  44 CSIT source code for the test cases used for plots can be found in
  45 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1810>`_.
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  51 3n-hsw-xl710
  52 ~~~~~~~~~~~~
  53
  54 64b-hw-base
  55 -----------
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  59     <center><b>
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  61 :index:`Speedup Multi-core: ipsec-3n-hsw-xl710-64b-base-ndr`
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  65     </b>
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  67     <p><br><br></p>
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  72     \begin{figure}[H]
  73         \centering
  74             \graphicspath{{../_build/_static/vpp/}}
  75             \includegraphics[clip, trim=0cm 0cm 5cm 0cm, width=0.70\textwidth]{ipsec-3n-hsw-xl710-64b-base-ndr-tsa}
  76             \label{fig:ipsec-3n-hsw-xl710-64b-base-ndr-tsa}
  77     \end{figure}
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  87 :index:`Speedup Multi-core: ipsec-3n-hsw-xl710-64b-base-pdr`
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  91     </b>
  92     <iframe id="ifrm02" onload="setIframeHeight(this.id)" width="700" frameborder="0" scrolling="no" src="../../_static/vpp/ipsec-3n-hsw-xl710-64b-base-pdr-tsa.html"></iframe>
  93     <p><br><br></p>
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  98     \begin{figure}[H]
  99         \centering
 100             \graphicspath{{../_build/_static/vpp/}}
 101             \includegraphics[clip, trim=0cm 0cm 5cm 0cm, width=0.70\textwidth]{ipsec-3n-hsw-xl710-64b-base-pdr-tsa}
 102             \label{fig:ipsec-3n-hsw-xl710-64b-base-pdr-tsa}
 103     \end{figure}
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 109 64b-hw-scale
 110 ------------
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 114     <center><b>
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 116 :index:`Speedup Multi-core: ipsec-3n-hsw-xl710-64b-scale-ndr`
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 120     </b>
 121     <iframe id="ifrm03" onload="setIframeHeight(this.id)" width="700" frameborder="0" scrolling="no" src="../../_static/vpp/ipsec-3n-hsw-xl710-64b-scale-ndr-tsa.html"></iframe>
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 127     \begin{figure}[H]
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 130             \includegraphics[clip, trim=0cm 0cm 5cm 0cm, width=0.70\textwidth]{ipsec-3n-hsw-xl710-64b-scale-ndr-tsa}
 131             \label{fig:ipsec-3n-hsw-xl710-64b-scale-ndr-tsa}
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 142 :index:`Speedup Multi-core: ipsec-3n-hsw-xl710-64b-scale-pdr`
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 146     </b>
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 148     <p><br><br></p>
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 153     \begin{figure}[H]
 154         \centering
 155             \graphicspath{{../_build/_static/vpp/}}
 156             \includegraphics[clip, trim=0cm 0cm 5cm 0cm, width=0.70\textwidth]{ipsec-3n-hsw-xl710-64b-scale-pdr-tsa}
 157             \label{fig:ipsec-3n-hsw-xl710-64b-scale-pdr-tsa}
 158     \end{figure}
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 164 64b-sw-base
 165 -----------
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 171 :index:`Speedup Multi-core: ipsec-3n-hsw-xl710-64b-sw-base-ndr`
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 186             \label{fig:ipsec-3n-hsw-xl710-64b-sw-ndr-tsa}
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 197 :index:`Speedup Multi-core: ipsec-3n-hsw-xl710-64b-sw-base-pdr`
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 208     \begin{figure}[H]
 209         \centering
 210             \graphicspath{{../_build/_static/vpp/}}
 211             \includegraphics[clip, trim=0cm 0cm 5cm 0cm, width=0.70\textwidth]{ipsec-3n-hsw-xl710-64b-sw-pdr-tsa}
 212             \label{fig:ipsec-3n-hsw-xl710-64b-sw-pdr-tsa}
 213     \end{figure}