lab: update Arm lab docs

[csit.git] / docs / report / introduction / methodology_multi_core_speedup.rst

diff --git a/docs/report/introduction/methodology_multi_core_speedup.rst b/docs/report/introduction/methodology_multi_core_speedup.rst
index 9484040..0530754 100644 (file)
--- a/docs/report/introduction/methodology_multi_core_speedup.rst
+++ b/docs/report/introduction/methodology_multi_core_speedup.rst
@@ -1,7 +1,7 @@
 Multi-Core Speedup
 ------------------
 
-All performance tests are executed with single processor core and with
+All performance tests are executed with single physical core and with
 multiple cores scenarios.
 
 Intel Hyper-Threading (HT)
@@ -14,9 +14,8 @@ applied in BIOS and requires server SUT reload for it to take effect,
 making it impractical for continuous changes of HT mode of operation.
 
 |csit-release| performance tests are executed with server SUTs' Intel
-XEON processors configured with Intel Hyper-Threading Disabled for all
-Xeon Haswell testbeds (3n-hsw) and with Intel Hyper-Threading Enabled
-for all Xeon Skylake testbeds.
+XEON processors configured with Intel Hyper-Threading Enabled
+for all Xeon Skylake and Xeon Cascadelake testbeds.
 
 More information about physical testbeds is provided in
 :ref:`tested_physical_topologies`.
@@ -27,15 +26,8 @@ Multi-core Tests
 |csit-release| multi-core tests are executed in the following VPP worker
 thread and physical core configurations:
 
-#. Intel Xeon Haswell testbeds (3n-hsw) with Intel HT disabled
-   (1 logical CPU core per each physical core):
-
-  #. 1t1c - 1 VPP worker thread on 1 physical core.
-  #. 2t2c - 2 VPP worker threads on 2 physical cores.
-  #. 4t4c - 4 VPP worker threads on 4 physical cores.
-
-#. Intel Xeon Skylake testbeds (2n-skx, 3n-skx) with Intel HT enabled
-   (2 logical CPU cores per each physical core):
+#. Intel Xeon Skylake and Cascadelake testbeds (2n-skx, 3n-skx, 2n-clx)
+   with Intel HT enabled (2 logical CPU cores per each physical core):
 
   #. 2t1c - 2 VPP worker threads on 1 physical core.
   #. 4t2c - 4 VPP worker threads on 2 physical cores.
@@ -51,7 +43,7 @@ In all CSIT tests care is taken to ensure that each VPP worker handles
 the same amount of received packet load and does the same amount of
 packet processing work. This is achieved by evenly distributing per
 interface type (e.g. physical, virtual) receive queues over VPP workers
-using default VPP round- robin mapping and by loading these queues with
+using default VPP round-robin mapping and by loading these queues with
 the same amount of packet flows.
 
 If number of VPP workers is higher than number of physical or virtual
@@ -62,5 +54,5 @@ for virtual interfaces are used for this purpose.
 Section :ref:`throughput_speedup_multi_core` includes a set of graphs
 illustrating packet throughout speedup when running VPP worker threads
 on multiple cores. Note that in quite a few test cases running VPP
-workers on 2 or 4 physical cores hits the I/O bandwidth or packets-per-
-second limit of tested NIC.
+workers on 2 or 4 physical cores hits the I/O bandwidth
+or packets-per-second limit of tested NIC.