Report: add 2n-tx2 static content

[csit.git] / docs / report / introduction / physical_testbeds.rst

diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst
index 8860638..3412e94 100644 (file)
--- a/docs/report/introduction/physical_testbeds.rst
+++ b/docs/report/introduction/physical_testbeds.rst
@@ -27,9 +27,10 @@ Current FD.io production testbeds are built with SUT servers based on
 the following processor architectures:
 
 - Intel Xeon: Skylake Platinum 8180, Haswell-SP E5-2699v3,
 the following processor architectures:
 
 - Intel Xeon: Skylake Platinum 8180, Haswell-SP E5-2699v3,

-  Cascadelake Platinum 8280, Cascadelake 6252N.
+  Cascade Lake Platinum 8280, Cascade Lake 6252N.

 - Intel Atom: Denverton C3858.
 - Intel Atom: Denverton C3858.

-- ARM: TaiShan 2280, hip07-d05.
+- Arm: TaiShan 2280, hip07-d05.
+- AMD EPYC: Zen2 7532.

 
 Server SUT performance depends on server and processor type, hence
 results for testbeds based on different servers must be reported
 
 Server SUT performance depends on server and processor type, hence
 results for testbeds based on different servers must be reported


@@ -41,13 +42,54 @@ https://git.fd.io/csit/tree/docs/lab/testbed_specifications.md.
 
 Following is the description of existing production testbeds.
 
 
 Following is the description of existing production testbeds.
 

-2-Node Xeon Cascadelake (2n-clx)
---------------------------------
+2-Node AMD EPYC Zen2 (2n-zn2)
+-----------------------------
+
+One 2n-zn2 testbed in in operation in FD.io labs. It is built based on
+two SuperMicro SuperMicro AS-1114S-WTRT servers, with SUT and TG servers
+equipped with one AMD EPYC Zen2 7532 processor each (256 MB Cache, 2.40
+GHz, 32 cores). 2n-zn2 physical topology is shown below.
+
+.. only:: latex
+
+    .. raw:: latex
+
+        \begin{figure}[H]
+            \centering
+                \graphicspath{{../_tmp/src/introduction/}}
+                \includegraphics[width=0.90\textwidth]{testbed-2n-zn2}
+                \label{fig:testbed-2n-zn2}
+        \end{figure}
+
+.. only:: html
+
+    .. figure:: testbed-2n-zn2.svg
+        :alt: testbed-2n-zn2
+        :align: center
+
+SUT server is populated with the following NIC models:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
+
+TG server runs TRex application and is populated with the following
+NIC models:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
+
+All AMD EPYC Zen2 7532 servers run with AMD SMT enabled, doubling the
+number of logical cores exposed to Linux.
+
+2-Node Xeon Cascade Lake (2n-clx)
+---------------------------------

 
 Three 2n-clx testbeds are in operation in FD.io labs. Each 2n-clx testbed
 is built with two SuperMicro SYS-7049GP-TRT servers, SUTs are equipped with two
 Intel Xeon Gold 6252N processors (35.75 MB Cache, 2.30 GHz, 24 cores).
 
 Three 2n-clx testbeds are in operation in FD.io labs. Each 2n-clx testbed
 is built with two SuperMicro SYS-7049GP-TRT servers, SUTs are equipped with two
 Intel Xeon Gold 6252N processors (35.75 MB Cache, 2.30 GHz, 24 cores).

-TGs are equiped with Intel Xeon Cascadelake Platinum 8280 processors (38.5 MB
+TGs are equiped with Intel Xeon Cascade Lake Platinum 8280 processors (38.5 MB

 Cache, 2.70 GHz, 28 cores). 2n-clx physical topology is shown below.
 
 .. only:: latex
 Cache, 2.70 GHz, 28 cores). 2n-clx physical topology is shown below.
 
 .. only:: latex


@@ -71,7 +113,7 @@ SUT servers are populated with the following NIC models:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.

-#. NIC-3: mcx556a-edat ConnectX5 2p100GE Mellanox. (Only testbed t27, t28)
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.

 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: empty, future expansion.
 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: empty, future expansion.


@@ -81,12 +123,12 @@ NIC models:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.

-#. NIC-3: mcx556a-edat ConnectX5 2p100GE Mellanox. (Only testbed t27, t28)
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.

 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
 
 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
 

-All Intel Xeon Cascadelake servers run with Intel Hyper-Threading enabled,
+All Intel Xeon Cascade Lake servers run with Intel Hyper-Threading enabled,

 doubling the number of logical cores exposed to Linux.
 
 2-Node Xeon Skylake (2n-skx)
 doubling the number of logical cores exposed to Linux.
 
 2-Node Xeon Skylake (2n-skx)


@@ -118,7 +160,7 @@ SUT servers are populated with the following NIC models:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.

-#. NIC-3: mcx556a-edat ConnectX5 2p100GE Mellanox. (Not used yet.)
+#. NIC-3: empty, future expansion.

 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: empty, future expansion.
 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: empty, future expansion.


@@ -128,7 +170,7 @@ NIC models:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.

-#. NIC-3: mcx556a-edat ConnectX5 2p100GE Mellanox. (Not used yet.)
+#. NIC-3: empty, future expansion.

 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
 #. NIC-4: empty, future expansion.
 #. NIC-5: empty, future expansion.
 #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)


@@ -344,8 +386,47 @@ SUT1 and SUT2 servers are populated with the following NIC models:
 #. NIC-1: connectx4 2p25GE Mellanox.
 #. NIC-2: x520 2p10GE Intel.
 
 #. NIC-1: connectx4 2p25GE Mellanox.
 #. NIC-2: x520 2p10GE Intel.
 

-TG servers run T-Rex application and are populated with the following
+TG server runs T-Rex application and is populated with the following
+NIC models:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: xl710-QDA2 2p40GE Intel.
+
+2-Node ARM ThunderX2 (2n-tx2)
+---------------------------
+
+One 2n-tx2 testbed is built with: i) one SuperMicro SYS-7049GP-TRT
+server acting as TG and equipped with two Intel Xeon Skylake Platinum
+8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one Marvell
+ThnderX2 9975 (28* ThunderX2) server acting as SUT and equipped with two
+ThunderX2 ARMv8 CN9975 processors. 2n-tx2 physical topology is shown below.
+
+.. only:: latex
+
+    .. raw:: latex
+
+        \begin{figure}[H]
+            \centering
+                \graphicspath{{../_tmp/src/introduction/}}
+                \includegraphics[width=0.90\textwidth]{testbed-2n-tx2}
+                \label{fig:testbed-2n-tx2}
+        \end{figure}
+
+.. only:: html
+
+    .. figure:: testbed-2n-tx2.svg
+        :alt: testbed-2n-tx2
+        :align: center
+
+SUT server is populated with the following NIC models:
+
+#. NIC-1: xl710-QDA2 2p40GE Intel.
+#. NIC-2: xl710-QDA2 2p40GE Intel.
+
+TG server run T-Rex application and is populated with the following

 NIC models:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.
 NIC models:
 
 #. NIC-1: x710-DA4 4p10GE Intel.
 #. NIC-2: xxv710-DA2 2p25GE Intel.

+#. NIC-3: xl710-QDA2 2p40GE Intel.