Current FD.io production testbeds are built with SUT servers based on
the following processor architectures:
-- Intel Xeon: Skylake Platinum 8180, Cascadelake 6252N, (Icelake 8358
- to be added).
+- Intel Xeon: Skylake Platinum 8180, Cascadelake 6252N, Icelake 8358.
- Intel Atom: Denverton C3858.
- Arm: TaiShan 2280, hip07-d05.
- AMD EPYC: Zen2 7532.
-CSIT-2106 report data for Intel Xeon Icelake testbeds comes from
-testbeds in Intel labs set up per CSIT specification and running CSIT
-code. Physical setup used is specified in 2n-icx and 3n-icx sections
-below. For details about tested VPP and CSIT versions
-see :ref:`vpp_performance_tests_release_notes`.
-
Server SUT performance depends on server and processor type, hence
results for testbeds based on different servers must be reported
separately, and compared if appropriate.
VPP is performance tested on SUTs with the following NICs and drivers:
-#. 2p10GE: x520, x550, x553 Intel (codename Niantic)
+#. 2p10GE: x550, x553 Intel (codename Niantic)
- DPDK Poll Mode Driver (PMD).
#. 4p10GE: x710-DA4 Intel (codename Fortville, FVL)
- DPDK PMD.
All Intel Xeon Cascadelake servers run with Intel Hyper-Threading enabled,
doubling the number of logical cores exposed to Linux.
-2-Node Xeon Icelake (2n-icx) EXPERIMENTAL
------------------------------------------
+.. _physical_testbeds_2n_icx:
+
+2-Node Xeon Icelake (2n-icx)
+----------------------------
-One 2n-icx testbed located in Intel labs was used for CSIT testing. It
-is built with two SuperMicro SYS-740GP-TNRT servers. SUT is equipped
-with two Intel Xeon Gold 6338N processors (48 MB Cache, 2.20 GHz, 32
-cores). TG is equiped with two Intel Xeon Ice Lake Platinum 8360Y
-processors (54 MB Cache, 2.40 GHz, 36 cores). 2n-icx physical topology
-is shown below.
+One 2n-icx testbed is in operation in FD.io labs. It is built with two
+SuperMicro SYS-740GP-TNRT servers, each in turn equipped with two Intel Xeon
+Platinum 8358 processors (48 MB Cache, 2.60 GHz, 32 cores).
.. only:: latex
SUT and TG NICs:
-#. NIC-1: E810-2CQDA2 2p100GbE Intel.
+#. NIC-1: xxv710-DA2 2p25GE Intel.
+#. NIC-2: E810-2CQDA2 2p100GbE Intel (* to be added).
+#. NIC-3: E810-CQDA4 4p100GbE Intel (* to be added).
All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
doubling the number of logical cores exposed to Linux.
-3-Node Xeon Icelake (3n-icx) EXPERIMENTAL
------------------------------------------
+.. _physical_testbeds_3n_icx:
-One 3n-icx testbed located in Intel labs was used for CSIT testing. It
-is built with three SuperMicro SYS-740GP-TNRT servers. SUTs are
-equipped each with two Intel Xeon Platinum 8360Y processors (54 MB
-Cache, 2.40 GHz, 36 cores). TG is equiped with two Intel Xeon Ice Lake
-Platinum 8360Y processors (54 MB Cache, 2.40 GHz, 36 cores). 3n-icx
-physical topology is shown below.
+3-Node Xeon Icelake (3n-icx)
+----------------------------
+
+One 3n-icx testbed is in operation in FD.io labs. It is built with three
+SuperMicro SYS-740GP-TNRT servers, each in turn equipped with two Intel Xeon
+Platinum 8358 processors (48 MB Cache, 2.60 GHz, 32 cores).
.. only:: latex
SUT and TG NICs:
-#. NIC-1: E810-2CQDA2 2p100GbE Intel.
+#. NIC-1: xxv710-DA2 2p25GE Intel.
+#. NIC-2: E810-2CQDA2 2p100GbE Intel (* to be added).
+#. NIC-3: E810-CQDA4 4p100GbE Intel (* to be added).
All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
doubling the number of logical cores exposed to Linux.
-2-Node Xeon Skylake (2n-skx)
-----------------------------
-
-Four 2n-skx testbeds are in operation in FD.io labs. Each 2n-skx testbed
-is built with two SuperMicro SYS-7049GP-TRT servers, each in turn
-equipped with two Intel Xeon Skylake Platinum 8180 processors (38.5 MB
-Cache, 2.50 GHz, 28 cores). 2n-skx physical topology is shown below.
-
-.. only:: latex
-
- .. raw:: latex
-
- \begin{figure}[H]
- \centering
- \graphicspath{{../_tmp/src/introduction/}}
- \includegraphics[width=0.90\textwidth]{testbed-2n-skx}
- \label{fig:testbed-2n-skx}
- \end{figure}
-
-.. only:: html
-
- .. figure:: testbed-2n-skx.svg
- :alt: testbed-2n-skx
- :align: center
-
-SUT NICs:
-
-#. NIC-1: x710-DA4 4p10GE Intel.
-#. NIC-2: xxv710-DA2 2p25GE Intel.
-#. NIC-3: empty, future expansion.
-#. NIC-4: empty, future expansion.
-#. NIC-5: empty, future expansion.
-#. NIC-6: empty, future expansion.
-
-TG NICs:
-
-#. NIC-1: x710-DA4 4p10GE Intel.
-#. NIC-2: xxv710-DA2 2p25GE Intel.
-#. NIC-3: empty, future expansion.
-#. NIC-4: empty, future expansion.
-#. NIC-5: empty, future expansion.
-#. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
-
-All Intel Xeon Skylake servers run with Intel Hyper-Threading enabled,
-doubling the number of logical cores exposed to Linux, with 56 logical
-cores and 28 physical cores per processor socket.
-
-3-Node Xeon Skylake (3n-skx)
-----------------------------
-
-Two 3n-skx testbeds are in operation in FD.io labs. Each 3n-skx testbed
-is built with three SuperMicro SYS-7049GP-TRT servers, each in turn
-equipped with two Intel Xeon Skylake Platinum 8180 processors (38.5 MB
-Cache, 2.50 GHz, 28 cores). 3n-skx physical topology is shown below.
-
-.. only:: latex
-
- .. raw:: latex
-
- \begin{figure}[H]
- \centering
- \graphicspath{{../_tmp/src/introduction/}}
- \includegraphics[width=0.90\textwidth]{testbed-3n-skx}
- \label{fig:testbed-3n-skx}
- \end{figure}
-
-.. only:: html
-
- .. figure:: testbed-3n-skx.svg
- :alt: testbed-3n-skx
- :align: center
-
-SUT1 and SUT2 NICs:
-
-#. NIC-1: x710-DA4 4p10GE Intel.
-#. NIC-2: xxv710-DA2 2p25GE Intel.
-#. NIC-3: empty, future expansion.
-#. NIC-4: empty, future expansion.
-#. NIC-5: empty, future expansion.
-#. NIC-6: empty, future expansion.
-
-TG NICs:
-
-#. NIC-1: x710-DA4 4p10GE Intel.
-#. NIC-2: xxv710-DA2 2p25GE Intel.
-#. NIC-3: empty, future expansion.
-#. NIC-4: empty, future expansion.
-#. NIC-5: empty, future expansion.
-#. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
-
-All Intel Xeon Skylake servers run with Intel Hyper-Threading enabled,
-doubling the number of logical cores exposed to Linux, with 56 logical
-cores and 28 physical cores per processor socket.
-
2-Node Atom Denverton (2n-dnv)
------------------------------
#. NIC-1: x710-DA4 4p10GE Intel.
+.. _physical_testbeds_3n_alt:
+
+3-Node ARM Altra (3n-alt)
+---------------------------
+
+One 3n-tsh testbed is built with: i) one SuperMicro SYS-740GP-TNRT
+server acting as TG and equipped with two Intel Xeon Icelake Platinum
+8358 processors (80 MB Cache, 2.60 GHz, 32 cores), and ii) one Ampere
+Altra server acting as SUT and equipped with two Q80-30 processors
+(80* ARM Neoverse N1). 3n-alt physical topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-3n-alt}
+ \label{fig:testbed-3n-alt}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-3n-alt.svg
+ :alt: testbed-3n-alt
+ :align: center
+
+SUT1 and SUT2 NICs:
+
+#. NIC-1: xl710-QDA2-2p40GE Intel.
+
+TG NICs:
+
+#. NIC-1: xxv710-DA2-2p25GE Intel.
+#. NIC-2: xl710-QDA2-2p40GE Intel.
+#. NIC-3: e810-XXVDA4-4p25GE Intel.
+#. NIC-4: e810-2CQDA2-2p100GE Intel.
+
3-Node ARM TaiShan (3n-tsh)
---------------------------
Code Review / csit.git / blobdiff