Report: Add RC1 data

[csit.git] / docs / report / introduction / test_environment_sut_calib_hsw.rst

diff --git a/docs/report/introduction/test_environment_sut_calib_hsw.rst b/docs/report/introduction/test_environment_sut_calib_hsw.rst
index b814988..d2e8d3d 100644 (file)
--- a/docs/report/introduction/test_environment_sut_calib_hsw.rst
+++ b/docs/report/introduction/test_environment_sut_calib_hsw.rst
@@ -1,35 +1,33 @@
-Calibration Data - Haswell
---------------------------
+Haswell
+~~~~~~~
 
 Following sections include sample calibration data measured on t1-sut1
 server running in one of the Intel Xeon Haswell testbeds as specified in
-`CSIT/Testbeds: Xeon Hsw, VIRL
-<https://wiki.fd.io/view/CSIT/Testbeds:_Xeon_Hsw,_VIRL.#FD.io_CSIT_testbeds_-_Xeon_Haswell.2C_VIRL>`_.
+`FD.io CSIT Testbeds - Xeon Haswell`_.
 
 Calibration data obtained from all other servers in Haswell testbeds
 shows the same or similar values.
 
-
 Linux cmdline
-~~~~~~~~~~~~~
+^^^^^^^^^^^^^
 
 ::
 
     $ cat /proc/cmdline
-    BOOT_IMAGE=/vmlinuz-4.15.0-36-generic root=UUID=5d2ecc97-245b-4e94-b0ae-c3548567de19 ro isolcpus=1-17,19-35 nohz_full=1-17,19-35 rcu_nocbs=1-17,19-35 numa_balancing=disable intel_pstate=disable intel_iommu=on iommu=pt nmi_watchdog=0 audit=0 nosoftlockup processor.max_cstate=1 intel_idle.max_cstate=1 hpet=disable tsc=reliable mce=off console=tty0 console=ttyS0,115200n8
+    BOOT_IMAGE=/vmlinuz-4.15.0-72-generic root=UUID=c59ae603-8076-41f4-bb5d-bc3fc8dd3ea1 ro isolcpus=1-17,19-35 nohz_full=1-17,19-35 rcu_nocbs=1-17,19-35 numa_balancing=disable intel_pstate=disable intel_iommu=on iommu=pt nmi_watchdog=0 audit=0 nosoftlockup processor.max_cstate=1 intel_idle.max_cstate=1 hpet=disable tsc=reliable mce=off console=tty0console=ttyS0,115200n8
 
 
 Linux uname
-~~~~~~~~~~~
+^^^^^^^^^^^
 
 ::
 
     $ uname -a
-    Linux t1-tg1 4.15.0-36-generic #39-Ubuntu SMP Mon Sep 24 16:19:09 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux
+    Linux t1-tg1 4.15.0-72-generic #81-Ubuntu SMP Tue Nov 26 12:20:02 UTC 2019 x86_64 x86_64 x86_64 GNU/Linux
 
 
 System-level Core Jitter
-~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -83,7 +81,7 @@ System-level Core Jitter
 
 
 Memory Bandwidth
-~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^
 
 ::
 
@@ -140,7 +138,7 @@ Memory Bandwidth
 
 
 Memory Latency
-~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^
 
 ::
 
@@ -200,7 +198,7 @@ Memory Latency
 
 
 L1/L2/LLC Latency
-~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^
 
 ::