#. 2port40GE VIC1385 Cisco.
#. 2port40GE XL710 Intel.
-For detailed LF FD.io test bed specification and physical topology please refer to `LF FDio CSIT testbed wiki page <https://wiki.fd.io/view/CSIT/CSIT_LF_testbed>`_.
+For detailed LF FD.io test bed specification and physical topology please refer
+to `LF FDio CSIT testbed wiki page <https://wiki.fd.io/view/CSIT/CSIT_LF_testbed>`_.
Performance Tests Coverage
--------------------------
- TRex setup introduces an always-on error of about 2*2usec per latency flow -
additonal Tx/Rx interface latency induced by TRex SW writing and reading
packet timestamps on CPU cores without HW acceleration on NICs closer to the
- interface line.
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+ interface line.