CSIT-1489: Change graphs to display results by suite generator

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / container_memif.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
index e770848..0ffeef5 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
@@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1810>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1901>`_.
 
 .. toctree::
 
@@ -22,4 +22,6 @@ CSIT source code for the test cases used for plots can be found in
     container_memif-3n-hsw-xl710
     container_memif-3n-skx-x710
     container_memif-2n-skx-x710
+
+..
     container_memif-2n-skx-xxv710