Report: Configure 1908.1.39

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / container_memif.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
index e770848..420a9eb 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
@@ -13,13 +13,13 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in

-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1810>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls1908>`_.

 
 .. toctree::
 
 
 .. toctree::
 

-    container_memif-3n-hsw-x520
-    container_memif-3n-hsw-x710
-    container_memif-3n-hsw-xl710
-    container_memif-3n-skx-x710
-    container_memif-2n-skx-x710

     container_memif-2n-skx-xxv710
     container_memif-2n-skx-xxv710

+    container_memif-3n-skx-xxv710
+    container_memif-3n-hws-xl710
+
+..
+    container_memif-3n-tsh-x520